STAMP0 datasheet(26/62 Pages) STMICROELECTRONICS

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Architecture

STAMP0

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DocID028639 Rev 1

4.6.2

Data transition or change

Data changes on the SDA line must only occur when the SCL clock is low. SDA transition

while the clock is high is used to identify a START or STOP condition.

4.6.3

Start condition

START is identified by a high to low transition of the data bus SDA signal while the clock

signal SCL is stable in the high state. A START condition must precede any command for

data transfer.

4.6.4

Stop condition

STOP is identified by a low to high transition of the data bus SDA signal while the clock

signal SCL is stable in the high state. A STOP condition terminates communication

between the slave and the bus master.

4.6.5

Data input

During the data input the slave samples the SDA signal on the rising edge of clock SCL.

For correct device operation the SDA signal must be stable during the rising edge of the

clock and the data can change only when the SCL line is low.

4.6.6

Device addressing

To start communication between the master and the slave, the master must initiate with a

start condition. Following this, the master sends 8 bits onto the SDA line (MSB first)

corresponding to the device select address and read or write mode. The 7 most significant

bits are the device address identifiers, corresponding to the I²C bus definition. The 8

th bit

(LSB) identifies read or write operation RW, this bit is set to 1 in read mode and 0 for write

mode. In the STAMP0 device, employing the SA pin, two possible device addresses can be

selected: 38 and 78. The former is selected by setting the SA pin equal to zero; the latter is

selected by setting the SA input pin equal to one.

After a START condition the slave identifies on the bus the device address and if a match

is found, it acknowledges the identification on the SDA bus during the 9

th bit time. The byte

following the device identification byte is the internal space address.

4.6.7

Write operation

Following the START condition the master sends a device select code with the RW bit set

to 0. The slave acknowledges this and then waits for the byte of the internal address. After

receiving the internal byte address, the slave again responds with an acknowledgement.

4.6.8

Byte write

In the byte write mode the master sends one data byte, this is acknowledged by the slave.

The master then terminates the transfer by generating a STOP condition.

4.6.9

Multi-byte write

The multi-byte write modes can start from any internal address. The master generating a

STOP condition terminates the transfer.

Obsolete

Product(s)

- Obsolete

Product(s)

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