6.3.2 Modulator

Figure 6-2 conceptualizes the second-order, switched-capacitor, feed-forward ΔΣ modulator implemented in the

AMC0106M05. The output V5 of the 1-bit, digital-to-analog converter (DAC) is subtracted from the input voltage

VIN = (VINP – VINN). This subtraction provides an analog voltage V1 at the input of the first integrator stage. The

output of the first integrator feeds the input of the second integrator stage. The result is an output voltage V3 that

is summed with the input signal VIN and the output of the first integrator V2. Depending on the polarity of the

resulting voltage V4, the output of the comparator is changed. In this case, the 1-bit DAC responds on the next

clock pulse by changing the associated analog output voltage V5. Thus, causing the integrators to progress in

the opposite direction and forcing the integrator output value to track the average value of the input.

VIN

Integrator 1

V1

V2

V4

V5

V3

fCLKIN

Σ

Integrator 2

Σ

+

–

DAC

0 V

DOUT

Figure 6-2. Block Diagram of a Second-Order Modulator

For reduced offset and offset drift, the integrators are chopper-stabilized with the chopping frequency set at

fCLKIN/16. Figure 6-3 shows the spur at 1.25MHz that is generated by the chopping frequency for a modulator

clock of 20MHz.

0.1

1

10

100

1000

10000

Frequency (kHz)

-180

-160

-140

-120

-100

-80

-60

-40

-20

0

G016

sinc3 filter, OSR = 1, fCLKIN = 20MHz, fIN = 1kHz

Figure 6-3. Quantization Noise Shaping

AMC0106M05

SBASAS7A – AUGUST 2024 – REVISED JUNE 2025

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