DS501-00024-6v1-E

13

MB85R4M2T

5. Write Cycle Timing 3 (Address Access and /WE Control)

6. Sleep Mode Timing

t

CAH

t

AS

A0 to A17

/ CE

/ LB,/ UB

Valid Address

Valid Address

t

WC

t

AX

t

WC

t

BS

Valid Address

t

AH

t

AX

t

PC

t

HZ

t

DS

t

DH

t

WZ

t

WP

t

WX

t

WP

t

AWH

t

AWH

t

WHA

t

WHA

* : In case the / OE is ・L・level, any bus conflict of input and output data shal l not occur.

Valid Output Data

Valid Input Data

Invalid Out put Data

/ WE

I/ O0 to I/ O15

XXX : H or L

* : In case the / OE is ・L・level, invalid data are output to data bus.

t

WX

t

DS

t

DH

t

WZ

t

BH

Valid Input Data

Invalid Output Data

Invalid Out put Data

t

WX

t

WZ

t

DS

t

DH

t

WP

t

WHA

Invalid Out put Data

t

PC

t

ZZL

t

ZZEX

/ WE

/ CE

/ ZZ

I/ O0 to I/ O15

t

ZZEN