ADS5294IPFPR datasheet(67/82 Pages) TI2

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CLKP

CLKM

Differential sine-

wave clock input

CLKP

CLKM

Differential

LVPECL

clock input

DIFFERENTIAL CLOCK CONNECTIONS

Rterm

CLKP

CLKM

Differential

LVDS

clock input

ADS529x

0.1 F

ADS529x

0.1 F

Rterm

ADS529x

Rterm

0.1 F

SINGLE-ENDED CLOCK CONNECTIONS

CLKP

CLKM

VCM

ADS529x

CMOS

CLOCK IN

ADS5294

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SLAS776E – NOVEMBER 2011 – REVISED APRIL 2018

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Typical Application (continued)

The ADS5294 clock input can be driven by either a differential clocks (sine wave, LVPECL, or LVDS) or a

singled clock(LVCMOS). In the single-ended case, TI recommends that the use of low jitter square signals

(LVCMOS levels, 1.8-V amplitude). See TI document SLYT075 for further details on the theory.

The jitter cleaner CDCM7005 SCAS793, CDCE72010 SLAS490, LMK04803 SNAS489 is suitable to generate the

ADC clock of the ADS5294 and ensure the performance for the14-bit ADC with >75-dBFS SNR. Please note that

the location of LVDS Rterm depends on the LVDS clock driver. Some clock devices require the Rterm at the left

side of AC coupling capacitors.

Figure 64. Single-Ended Clock Drive Circuit

Figure 65. Differential Clock Drive Circuit

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