ADV7182ABCPZ datasheet(20/102 Pages) AD

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ADV7182A

Data Sheet

Rev. 0 | Page 20 of 102

GLOBAL STATUS REGISTERS

Four registers provide summary information about the video

decoder. The IDENT register allows the user to identify the

revision code of the ADV7182A. The other three registers

(Address 0x10, Address 0x12, and Address 0x13) contain

status bits from the ADV7182A.

IDENTIFICATION REGISTER

IDENT[7:0]—Address 0x11, Bits[7:0]

This is the register identification of the ADV7182A revision.

Table 17 describes the various versions of the ADV7182A.

Table 17. IDENT[7:0] CODE

IDENT[7:0]

Description

0x40

Prerelease silicon

0x41

Released silicon

STATUS 1 REGISTER

Status 1[7:0]—Address 0x10, Bits[7:0]

This read only register provides information about the internal

status of the ADV7182A.

See the CIL[2:0], Count in to Lock—Address 0x51, Bits[2:0]

section and the COL[2:0], Count Out of Lock (COL)—Address

0x51, Bits[5:3] section for details on timing.

Depending on the setting of the FSCLE bit, the status registers are

based solely on horizontal timing information or on the horizontal

timing and lock status of the color subcarrier. See the FSCLE,

fSC Lock Enable—Address 0x51, Bit 7 section.

See the Autodetection of SD Modes section for a description of

the AD_RESULT bits.

Table 18. Status 1 Function

Status 1[7:0]

Bit Name

Description

IN_LOCK

In lock (now)

LOST_LOCK

Lost lock (since last read)

FSC_LOCK

fSC locked (now)

FOLLOW_PW

AGC follows peak white algorithm

AD_RESULT[0]

Result of autodetection

AD_RESULT[1]

Result of autodetection

AD_RESULT[2]

Result of autodetection

COL_KILL

Color kill active

STATUS 2 REGISTER

Status 2[7:0]—Address 0x12, Bits[7:0]

Table 19. Status 2 Function

Status 2[7:0]

Bit Name

Description

MVCS DET

Detected Rovi color striping

MVCS T3

Rovi color striping protection;

conforms to Type 3 if high, Type

2 if low

MV PS DET

Detected Rovi pseudo sync

pulses

MV AGC DET

Detected Rovi AGC pulses

LL NSTD

Line length is nonstandard

FSC NSTD

fSC frequency is nonstandard

Reserved

STATUS 3 REGISTER

Status 3[7:0]—Address 0x13, Bits[7:0]

Table 20. Status 3 Function

Status 3[7:0]

Bit Name

Description

INST_HLOCK

Horizontal lock indicator

(instantaneous)

Reserved

SD_OP_50Hz

Flags whether 50 Hz or 60 Hz is

present at output

Reserved

FREE_RUN_ACT

Flags if the ADV7182A entered

freerun mode (see the Freerun

Operation section)

STD FLD LEN

Field length is correct for

currently selected video

standard

Interlaced

Interlaced video detected

(field sequence found)

PAL_SW_LOCK

Reliable sequence of

swinging bursts detected

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