ADV7182ABCPZ datasheet(63/102 Pages) AD

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Data Sheet

ADV7182A

Rev. 0 | Page 63 of 102

ITU-R BT.656 Tx CONFIGURATION

The ADV7182A receives analog video and outputs digital video

according to the ITU-R BT.656 specification. The ADV7182A

outputs the ITU-R BT.656 video data stream over the P0 to P7

data pins and has a line locked clock (LLC) pin and two

synchronization pins (HS and VS/FIELD/SFL).

Video data is output over the P0 to P7 pins in YCrCb 4:2:2

format. Synchronization signals are automatically embedded in

the video data signal in accordance with the ITU-R BT.656

specification.

The LLC output is used to clock the output data on the P0 to P7

pins at a nominal frequency of 27 MHz.

The two synchronization pins (HS and VS/FIELD/SFL) output

a variety of synchronization signals such as horizontal sync,

vertical sync, field sync, and color subcarrier frequency lock

(SFL) sync. The majority of these synchronization signals are

already embedded in the video data. Therefore, the use of the

synchronization pins is optional.

The following registers can be used to configure the ITU-R

BT.656 output from the ADV7182A. See the Global Control

Registers section for further registers that can be used to

configure the output from the ADV7182A.

SWPC, Swap Pixel Cr/Cb—Address 0x27, Bit 7

This bit allows Cr and Cb samples to be swapped.

When SWPC is 0 (default), no swapping is allowed. When SWPC

is 1, the Cr and Cb values can be swapped.

Polarity LLC Pin

PCLK—Address 0x37, Bit 0

The polarity of the clock that leaves the ADV7182A via the

LLC pin can be inverted using the PCLK bit. Changing the

polarity of the LLC clock output may be necessary to meet the

setup and hold time expectations of follow-on chips. When

PCLK is 0, the LLC output polarity is inverted. When PCLK is 1

(default), the LLC output polarity is normal (see the Timing

Specifications section.)

LLC_PAD_SEL[2:0] LLC Output Selection—

Address 0x8F, Bits[6:4]

The following I2C write allows the user to select between LLC

(nominally at 27 MHz) and LLC (nominally at 13.5 MHz).

When LLC_PAD_SEL is 000, the output is nominally 27 MHz

LLC on the LLC pin (default).

When LLC_PAD_SEL is 101, the output is nominally 13.5 MHz

LLC on the LLC pin.

BT.565-4, ITU-R BT.565-3/ITU-R BT.565-4 Enable—

Address 0x04, Bit 7

Between Revision 3 and Revision 4 of the ITU-R BT.656 standards,

the toggling position for the V bit within the SAV EAV codes

for NTSC has changed. Note that the standard change affects

only NTSC and has no bearing on PAL. For further information,

visit the International Telecommunication Union website.

The BT.656-4 bit allows the user to select an output mode that is

compliant with either the ITU-R BT.656-3 standard or ITU-R

BT.656-4 standard.

When the BT.656-4 bit is set to 0 (default), the ITU-R BT.656-3

specification is used. The V bit goes low at EAV of Line 10 and

Line 273.

When ITU-R BT.656-4 is 1, the ITU-R BT.656-4 specification is

used. The V bit goes low at EAV of Line 20 and Line 283.

Figure 45. ITU-R BT.656 Output Stage of the ADV7182A

(OPTIONAL)

VS/FIELD/SFL

(OPTIONAL)

ITU-R BT.656

DATA

STREAM

VIDEO

DECODER

ANALOG

VIDEO

INPUT

LLC

ADV7182A

STANDARD

DEFINITION

PROCESSOR

ANALOG

FRONT

END

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