LP8754 datasheet(10/52 Pages) TI2

10 / 52 page

LP8754

SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014

www.ti.com

6-Phase Buck System Characteristics (continued)

Limits apply over the full ambient temperature range -40°C

≤ TA ≤ 85°C, VVDDA5V = VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V,

VOUT = 1.1 V, (unless otherwise noted).

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Input capacitance on each input

Effective capacitance during operation, 2.5 V

≤

CIN

2.5

µF

voltage rail (5) (4)

VVINBXX ≤ 5 V, Min value over TA –40°C to 85°C

Output inductance

Effective inductance during operation

0.25

0.47

µH

IBALANCE

Current balancing accuracy

IOUT ≥ 1000 mA

< 10%

COUT ESR = 10 mΩ

VRIPPLE_P Output voltage ripple PWM mode,

PWM mode, IOUT = 200 mA

mVPP

One phase active(6)

Switching frequency = 3 MHz

COUT ESR = 10 mΩ

VRIPPLE_P Output voltage ripple PFM

PFM mode

mVPP

mode(6)

IOUT = 100 µA

COUT ESR = 10 mΩ

VRIPPLE_L Output Voltage Ripple Low-Power

Low-power PFM mode

mVPP

PFM mode(6)

IOUT = 100 µA

(5)

In addition to these capacitors, at least one higher value capacitor (for example 22 µF) should be placed close to the power pins. Note

that cores B0-B1 and B3-B4 do have combined power input pins.

(6)

Ripple voltage should be measured at COUT electrode on a well-designed PCB, using suggested inductors and capacitors and with a

high-quality scope probe.

6.8 Protection Features Characteristics

Limits apply over the full ambient temperature range -40°C

≤ TA ≤ 85°C, VVDDA5V = VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V,

VOUT = 1.1 V, (unless otherwise noted).

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOLTAGE MONITORING

Power good threshold for voltage

VPG

Power good threshold voltage

90%

decreasing, % of setting, VOUT = 1.1 V

Input overvoltage protection trigger

VIN rising. Voltage monitored on VDDA5V

VOVP

5.15

5.30

5.45

point (1)(2)

Input undervoltage lockout (UVLO)

VIN falling. Voltage monitored on VDDA5V

VUVLO

2.15

2.25

2.35

turn-on threshold (1)

Detected by sensing the voltage on

VSCP

Output short-circuit fault threshold

400

converter output with respect to GND.

Triggered by converter start-up, specified by

tMASKSCP

SCP masking time

400

µs

design

Triggered by converter start-up, specified by

400

µs

design

Triggered by VSET transition, specified by

design

Slew Rate setting mV/µs

100

tMASKPG

Power Good masking time

7.5

200

3.8

400

µs

1.9

800

0.94

1600

0.47

3200

0.23

6400

(1)

Undervoltage lock-out (UVLO) and overvoltage protection (OVP) circuits shut down the LP8754 when the system input voltage is

outside the desired operating range.

(2)

Limits for OVP trigger points apply when VVIOSYS is high. False OVP alarm may occur, if the input voltage rises close to 5 V while

VVIOSYS is low.

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