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LP8754 bảng dữ liệu(PDF) 4 Page - Texas Instruments |
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LP8754 bảng dữ liệu(HTML) 4 Page - Texas Instruments |
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4 / 52 page ![]() LP8754 SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 www.ti.com Pin Functions (continued) PIN TYPE DESCRIPTION NUMBER NAME Remote sensing (negative). Connect to the respective sense pin of the processor or to the D5 FBB0 −/B1 A negative power supply trace of the processor as close as possible to the processor. Remote sensing (positive). Connect to the respective sense pin of the processor or to the D6 FBB0+/B0 A positive power supply trace of the processor as close as possible to the processor. D7 GNDA G Ground Serial Interface data input and output for Dynamic Voltage Scaling (DVS). Connect a pull-up E1 SDASR D/I/O resistor / connect to GND if not used. Serial Interface clock input for Dynamic Voltage Scaling (DVS). Connect a pull-up resistor / E2 SCLSR D/I connect to GND if not used. E3, F3, G3 GNDB4/B5 G Power Ground for Buck 4 and Buck 5 Voltage reference input for Dynamic Voltage Scaling (DVS) interface. Setting NRST input HIGH E4 NRST A triggers start-up sequence. Input for Buck 3 and Buck 4.The separate power pins VINBXX are not connected together E5, F5, G5 VINB3/B4 P internally - VINBXX pins must be connected together in the application and be locally bypassed. E6 INT D/O Open-drain interrupt output. Active LOW. Connect a pull-up resistor to I/O supply. This pin shall be tied to the system I/O-voltage. Bias supply voltage for the device. Enables the I/O interface: All registers are accessible via serial bus interface when this pin is pulled high. An E7 VIOSYS A internal power-on reset (POR) occurs when VIOSYS is toggled low/high. The I2C host should allow at least 500 µs before sending data to the LP8754 after the rising edge of the VIOSYS line. F1 VDDA5V P Input for Analog blocks F2, G2 SWB5 A Buck 5 switch node F4, G4 SWB4 A Buck 4 switch node F6, G6 SWB3 A Buck 3 switch node F7, G7 GNDB3 G Power Ground for Buck 3 Input for Buck 5. The separate power pins VINBXX are not connected together internally - G1 VINB5 P VINBXX pins must be connected together in the application and be locally bypassed. A: Analog Pin, D: Digital Pin, G: Ground Pin, P: Power Pin, I: Input Pin, O: Output Pin 4 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 |
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