Micromirror Landed Duty Cycle

0/100 5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55

30

40

50

60

70

80

D001

50/50

100/0

95/5

90/10

85/15

80/20

75/25

70/30

65/35

60/40

55/45

Figure 6-1. Max Recommended Array Temperature—Derating Curve

6.5 Thermal Information

THERMAL METRIC(1)

DLP2000

UNIT

FQC (LGA)

42 PINS

Thermal resistance active area to test point 1 (TP1) (1)

8

°C/W

(1)

The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of

maintaining the package within the temperature range specified in Section 6.4. The total heat load on the DMD is largely driven by

the incident light absorbed by the active area; although other contributions include light energy absorbed by the window aperture and

electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling outside the window

aperture since any additional thermal load in this area can significantly degrade the reliability of the device.

6.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOH

High level output voltage

VCC = 1.65 V

IOH = –2 mA

1.20

V

VOL

Low level output voltage

VCC = 1.95 V

IOL = –2 mA

0.45

V

IIL

Low level input current(1) (2)

VCC = 1.95 V

VI = 0 V

52

nA

IIH

High level input current(1) (2)

VCC = 1.95 V

VI = 1.95 V

41

nA

CURRENT

ICC

Current at VCC = 1.95 V

DCLK Frequency = 77 MHz

30

mA

IOFFSET

Current at VOFFSET = 8.75 V(3)

1.5

mA

IBIAS

Current at VBIAS = 16.5 V(3) (4) Three global resets within time period = 200 µs

1.3

mA

IRESET

Current at VRESET = –10.5 V

Three global resets within time period = 200 µs

1.2

mA

POWER

PCC

Power at VCC = 1.95 V(5)

DCLK Frequency = 77 MHz

26

59

mW

POFFSET

Power at VOFFSET = 8.75 V(5)

5

13

mW

PBIAS

Power at VBIAS = 16.5 V(5)

Three global resets within time period = 200 µs

9

22

mW

PRESET

Power at VRESET = –10.5 V(5)

Three global resets within time period = 200 µs

4

13

mW

PTOTAL

Supply power dissipation total

44

107

mW

CAPACITANCE

CIN

Input capacitance

f = 1 MHz

10

pF

DLP2000

DLPS140B – MARCH 2019 – REVISED MAY 2022

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