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DLP2000AFQC bảng dữ liệu(PDF) 4 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  DLP2000 (.2 nHD) DMD
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DLP2000AFQC bảng dữ liệu(HTML) 4 Page - Texas Instruments

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Table 5-1. Pin Functions (continued)
PIN
TYPE
SIGNAL
DATA
RATE
DESCRIPTION
PACKAGE NET
LENGTH (mm)
NAME
NO.
SCTRL
K12
Input
LVCMOS
DDR
Serial control (sync)
8.62
DRC_BUS
K14
Input
LVCMOS
Reset control serial bus. synchronous to
rising edge of DCLK. Bond pad does not
connect to internal pull down.
7.28
DRC_OEZ
K18
Input
LVCMOS
Active low. Output enable signal for internal
reset driver circuitry. Bond pads do not
connect to internal pulldown.
4.69
DRC_STROBE
J15
Input
LVCMOS
Rising edge on DRC_STROBE latches in
the control signals. Synchronous to rising
edge of DCLK. Bond pad does not connect
to internal pulldown.
7.61
SAC_BUS
K16
Input
LVCMOS
Stepped address control serial bus.
Synchronous to rising edge of DCLK. Bond
pad does not connect to internal pulldown.
8.17
SCAN_TEST
K20
Input
LVCMOS
MUX’ed output for scanned chip ID
1.18
POWER
VBIAS
J16
Power
Power supply for positive bias level of
mirror reset signal
VOFFSET
K15
Power
Power supply for high voltage CMOS logic.
Power supply for stepped high voltage at
mirror address electrodes. Power supply for
offset level of mirror reset signal
VRESET
J20
Power
Power supply for negative reset level of
mirror reset signal
VCC
J1
Power
Power supply for low voltage CMOS logic.
Power supply for normal high voltage at
mirror address electrodes. Power supply
for offset level of mirror reset signal during
power down
VCC
J11
Power
VCC
J21
Power
VCC
K1
Power
VCC
K11
Power
VCC
K21
Power
VSS
J3
Power
Common return. Ground for all power
VSS
J5
Power
VSS
J9
Power
VSS
J14
Power
VSS
J17
Power
VSS
J18
Power
VSS
J19
Power
VSS
K3
Power
VSS
K5
Power
VSS
K8
Power
VSS
K13
Power
VSS
K17
Power
VSS
K19
Power
DLP2000
DLPS140B – MARCH 2019 – REVISED MAY 2022
www.ti.com
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