8.2.2.3 Application Curve

8.3 Power Supply Recommendations

Always apply a ground reference to the GND pins first. This device is designed for glitch free power sequencing

without any ramp order requirements.

This device was designed with various power supply sequencing methods in mind to help prevent unintended

triggering of downstream devices, as described in Glitch-free Power Supply Sequencing.

8.3.1 Power-Up Consideration

Each VCC pin must have a good bypass capacitor to prevent power disturbance. For devices with a single

supply, 0.1µF is recommended. If there are multiple VCC pins, 0.01µF or 0.022µF is recommended for each

power pin. It is acceptable to parallel multiple bypass capacitors to reject different frequencies of noise. 0.1µF

and 1µF capacitors are commonly used in parallel. The bypass capacitor must be installed as close to the power

pin as possible for best results.

Table 8-4. Typical Total Static Power Consumption (ICCA + ICCB)

VCCB

VCCA

UNIT

0V

1.8V

2.5V

3.3V

5V

0V

0

< 1

< 1

< 1

< 1

µA

1.8V

< 1

< 2

< 2

< 2

2

2.5V

< 1

< 2

< 2

< 2

< 2

3.3V

< 1

< 2

< 2

< 2

< 2

5V

< 1

2

< 2

< 2

< 2

8.4 Layout

8.4.1 Layout Guidelines

It is recommended to follow common printed-circuit board layout guidelines for device reliability, such as the

follows:

• Use bypass capacitors on the power supplies.

• Use short trace lengths to avoid excessive loading.

• Place pads on the signal paths for loading capacitors or pullup resistors to help adjust rise and fall times of

signals depending on the system requirements.

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SN74LVC2T45-Q1

SCES818C – SEPTEMBER 2010 – REVISED JULY 2024

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