8.2.2 Bidirectional Logic Level-Shifting Application

Figure 8-2 shows the SN74LVC2T45-Q1 being used in a bidirectional logic level-shifting application. Because

the SN74LVC2T45-Q1 does not have an output-enable (OE) pin, the system designer should take precautions to

avoid bus contention between SYSTEM-1 and SYSTEM-2 when changing directions.

VCC1

VCC1

VCC2

SYSTEM-1

SYSTEM-2

1

2

3

4

8

7

6

5

DIR CTRL

I/O-1

Pullup/Down

or Bus Hold(1)

VCC2

I/O-2

Pullup/Down

or Bus Hold(1)

Figure 8-2. Bidirectional Logic Level-Shifting Application

8.2.2.1 Design Requirements

Refer to Section 8.2.1.

8.2.2.2 Detailed Design Procedure

Table 8-3 provides data transmission from SYSTEM-1 to SYSTEM-2 and then from SYSTEM-2 to SYSTEM-1.

Table 8-3. Data Transmission Sequence

STATE

DIR CTRL

I/O-1

I/O-2

DESCRIPTION

1

H

Out

In

SYSTEM-1 data to SYSTEM-2

2

H

Hi-Z

Hi-Z

SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1 and I/O-2 are disabled. The

bus-line state depends on pullup or pulldown.(1)

3

L

Hi-Z

Hi-Z

DIR bit is flipped. I/O-1 and I/O-2 still are disabled. The bus-line state depends on pullup or

pulldown.(1)

4

L

In

Out

SYSTEM-2 data to SYSTEM-1

(1)

SYSTEM-1 and SYSTEM-2 must use the same conditions, that is, both pullup or both pulldown.

8.2.2.2.1 Enable Times

Calculate the enable times for the SN74LVC2T45-Q1 using the following formulas:

• tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)

• tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)

• tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B)

• tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B)

In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is

switched until an output is expected. For example, if the SN74LVC2T45-Q1 initially is transmitting from A to B,

then the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After

the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified

propagation delay.

SN74LVC2T45-Q1

SCES818C – SEPTEMBER 2010 – REVISED JULY 2024

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