ZL40262 datasheet(16/36 Pages) MICROCHIP

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ZL40262

DS20006843A-page 16



2024 Microchip Technology Inc. and its subsidiaries.

—

TABLE 3-4:

INPUT CHARACTERISTICS

Note 1, Note 2, Note 3

Parameter

Symbol

Min

Typ.

Max

Units Condition

CMOS high-level input voltage for control

inputs

VCIH_3.3V

0.7 ×

VDD

—

VDD = 3.3V

VCIH_2.5V

0.8 ×

VDD

—

VDD = 3.3V

CMOS low-level input voltage for control inputs

VCIL

—

0.32 ×

VDD

—

CMOS input leakage current for control inputs

(includes current due to pull down resistors)

IIL

–25

—

µA

VI = VDD or 0V

Differential input common mode voltage for

IN_p/n

VCM

0.1

—

0.8

—

Differential input voltage for IN_p/n

VID

0.2

—

VDD +

0.3

—

Differential input leakage current for IN_p/n

(includes current due to pull-up and pull-down

resistors)

IIL

–150

—

150

µA

VI = 2V or 0V

Single ended input voltage for IN_p

VSI

–0.3

—

2.7

VDD = 3.3V or 2.5V

Single ended input common mode voltage

IN_p

VSIC

0.1

—

0.8

VDD = 3.3V or 2.5V

Single ended input voltage swing for IN_p

VSID

0.3

—

1.3

VDD = 3.3V or 2.5V

Input frequency (differential)

fIN

—

400

MHz —

Input duty cycle

—

Input slew rate

slew

0.6

—

V/ns —

Input pull-up/pull-down resistance

RPU/RPD

—

kΩ

—

Input pull-down resistance for IN_p

RPD

—

kΩ

—

Control input (OE_b) pull-down resistance

RPDOE

—

300

—

kΩ

—

Note 1: Values are over recommended operating conditions.

2: Values are over all two power supply modes (VDD = 3.3V and VDD = 2.5V).

3: Low frequency only.

TABLE 3-5:

POWER SUPPLY REJECTION RATIO FOR VDD = VDDO = 3.3V

Note 1, Note 2, Note 3

Parameter

Symbol

Min

Typ.

Max

Units Condition

PSRR for HCSL output

PSRRHCSL

—

–80.7

—

dBc

fIN = 100 MHz

–76.4

fIN = 133 MHz

–66.5

fIN = 400 MHz

Note 1: Values are over recommended operating conditions.

2: Noise injected to VDD/VDDO power supply with frequency 100 kHz and amplitude 100 mVpp.

3: PSRR is measured as amplitude of 100 kHz spur in dBc on the output clock phase noise plot.

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