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ZL40262 bảng dữ liệu(PDF) 12 Page - Microchip Technology

tên linh kiện ZL40262
Giải thích chi tiết về linh kiện  Two Output Ultra-Low Additive Phase Noise PCIe
PDF  36 Pages
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nhà sản xuất  MICROCHIP [Microchip Technology]
Trang chủ  http://www.microchip.com
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ZL40262 bảng dữ liệu(HTML) 12 Page - Microchip Technology

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ZL40262
DS20006843A-page 12
2024 Microchip Technology Inc. and its subsidiaries.
2.3
Termination of Unused Inputs and Outputs
Unused outputs should be left unconnected.
2.4
Power Consumption
The device total power consumption can be calculated as:
EQUATION 2-1:
Where:
Power dissipated inside the device can be calculated by subtracting power dissipated in termination/biasing resistors
from the power consumption:
EQUATION 2-2:
Where:
2.5
Power Supply Filtering
Each power pin (VDD and VDDO) should be decoupled with 0.1 µF capacitor with minimum equivalent series resistance
(ESR) and minimum series inductance (ESL). For example, 0402 X5R Ceramic Capacitors with 6.3V minimum rating
could be used. These capacitors should be placed as close as possible to the power pins. To reduce the power noise
from adjacent digital components on the board, each power supply could optionally be further insulated with low resis-
tance ferrite bead with 10 µF and 1 µF capacitors. Figure 2-8 shows the standard and optional decoupling method.
PS = VDD × IS
Core power consumed by the input buffer. The static cur-
rent (IS) is specified in Table 4.
PC = VDDO × IDD_CM
Common output power shared between two outputs. The
current IDD_CM is specified in Table 4.
PO_DIF = VDDO × IDD_HCSL × N
Output power where output current per output
(IDD_HCSL) is specified in Table 4.
N is number of enabled outputs.
PHCSL = (VSW / 50Ω)2 x (50Ω + 33Ω)
VSW is voltage swing of HCSL output. 50Ω is termination
resistance and 33Ω is series resistance of the HCSL out-
put.
PT PS PC PO_DIFF
+
+
=
PD PT N PHCSL
–
=



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