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DS20006363D-page 23

SY75608/612

5.0

HOST INTERFACE

SY75608 and SY75612 can be controlled via hardware pins (SEL pin tied low) or via I2C Bus (SEL pin tied high). The

mode shall be selected during power up and it cannot be changed on the fly.

5.1

Hardware Controlled Mode

In this mode, SY75608/612 is controlled via Input Select pins (IN_SEL[1:0]) that select which one of three inputs is fed

to outputs (as shown in Table 5-1), output enable pins (OE_b) for each output (as shown in Figure 5-1), and Output

Impedance Select pin.

Any outputs can be disabled by pulling the corresponding OExb pin high. The OExb is sampled on the falling edge of

the differential input clock (or falling edge of INx_p). It takes 4.5 clock cycles before the output goes from the active state

to the state defined by OE_TYPE0/1 pins (SEL = 0) or defined by DRVSTATE0/1/2 register (SEL = 1) as shown in

Figure 5-1.

FIGURE 5-1:

Output Disable.

Any outputs can be enabled by pulling the corresponding OExb pin low. The OExb is sampled on the falling edge of the

differential input (or falling edge of Inx_p signal). It takes 3.5 clock cycles of the input clock before the output goes from

the state defined by OE_TYPE0/1 pins (SEL pin pulled low) or defined by DRVSTATE0/1/2 registers (SEL pin pulled

high) to the active state as shown in Figure 5-2.

TABLE 5-1:

INPUT CLOCK SELECTION

IN_SEL1

IN_SEL0

Selected Input

0

0

IN0_p, IN0_n

0

1

IN1_p, IN1_n

1

X

XIN (crystal input pin)

INx_n

INx_p

INx_p - INx_n

OExb

OUTx_n

OUTx_p

OUTx_n

OUTx_p

If OExb are selected to tristate outputs

If OExb are selected to pull-low through

series termina on resistor (HCSL default)

OUTx_n

OUTx_p

If OExb are selected to drive low

I/O delay

OUTx_n

OUTx_p