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PIC12LF1552 bảng dữ liệu(PDF) 49 Page - Microchip Technology |
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PIC12LF1552 bảng dữ liệu(HTML) 49 Page - Microchip Technology |
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49 / 356 page  2015-2016 Microchip Technology Inc. Preliminary DS40001817B-page 49 PIC16LF1566/1567 Bank 31 F80h INDF0(1) Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx uuuu uuuu F81h INDF1(1) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx uuuu uuuu F82h PCL(1) Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 F83h STATUS(1) — — —TO PD ZDC C ---1 1000 ---q quuu F84h FSR0L(1) Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu F85h FSR0H(1) Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 F86h FSR1L(1) Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu F87h FSR1H(1) Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 F88h BSR(1) — — — BSR<4:0> ---0 0000 ---0 0000 F89h WREG(1) Working Register 0000 0000 uuuu uuuu F8Ah PCLATH(1) — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 F8Bh INTCON(1) GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000 F8Ch ICDIO PORT_ ICDDAT PORT_ ICDCLK LAT_ ICDDAT LAT_ ICDCLK TRIS_ ICDDAT TRIS_ ICDCLK — — xxxxxx-- F8Dh ICDCON0 INBUG FREEZ SSTEP —DBGINEX — — RSTVEC xxx-x--x F8Eh to F90h — Unimplemented — — F91h ICDSTAT TRP1HLTF TRP0HLTF — — — — USRHLTF — xx----x- F92h to F95h — Unimplemented — — F96h ICDINSTL DBGIN7 DBGIN6 DBGIN5 DBGIN4 DBGIN3 DBGIN2 DBGIN1 DBGIN0 xxxxxxxx F97h ICDINSTH — — DBGIN13 DBGIN12 DBGIN11 DBGIN10 DBGIN9 DBGIN8 --xxxxxx F98h to F9Bh — Unimplemented — — F9Ch ICDBK0CON BKEN — — — — — — BKHLT x------x F9Dh ICDBK0L BKA7 BKA6 BKA5 BKA4 BKA3 BKA2 BKA1 BKA0 xxxxxxxx F9Eh ICDBK0H — BKA14 BKA13 BKA12 BKA11 BKA10 BKA9 BKA8 -xxxxxxx F9Fh — Unimplemented — — FA0h to FBFh — Unimplemented — — FC0h to FCFh — Unimplemented — — FD0h to FE2h — Unimplemented — — FE3h BSRICDSHAD — — — BSR_ICDSHAD ---xxxxx — FE4h STATUS_- SHAD — — — — — Z_SHAD DC_SHAD C_SHAD ---- -xxx ---- -uuu FE5h WREG_SHAD WREG_SHAD xxxx xxxx uuuu uuuu FE6h BSR_SHAD — — — BSR_SHAD ---x xxxx ---u uuuu FE7h PCLATH_- SHAD — PCLATH_SHAD -xxx xxxx uuuu uuuu FE8h FSR0L_SHAD FSR0L_SHAD xxxx xxxx uuuu uuuu FE9h FSR0H_SHAD FSR0H_SHAD xxxx xxxx uuuu uuuu FEAh FSR1L_SHAD FSR1L_SHAD xxxx xxxx uuuu uuuu FEBh FSR1H_SHAD FSR1H_SHAD xxxx xxxx uuuu uuuu TABLE 3-11: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Addr. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Note 1: These registers can be accessed from any bank. 2: PIC16LF1567. 3: These registers/bits are available at two address locations, in Bank 1 and Bank 14. 4: PIC16LF1566 only. 5: Unimplemented, read as ‘1’. |
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