TDA8026ETSLASHC2 datasheet(32/61 Pages) NXP

32 / 61 page

TDA8026_1

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Product data sheet

Rev. 1.1 — 30 June 2016

32 of 61

NXP Semiconductors

TDA8026

Multiple smart card slot interface IC

8.5.6.3

Bank 1 Interrupt register (address 42h; CSb[7:0] = 00h) read mode bit descriptions

[1]

The INTx numbers do not match the bit positions and are as follows:

bit 4 = INT5, bit 3 = INT4, bit 2 = INT3, bit 1 = INT2 and bit 0 = INT1

8.5.6.4

Bank 1 Slew rate register (address 40h; CSb[7:0] = 06h) read/write mode bit

descriptions

Refer Section 8.10 on page 38 for more detailed information.

Table 36.

Bank 1 Interrupt register (address 42h; CSb[7:0] = 00h) read mode bit

descriptions

Bit

Symbol

Value

Description

7 to 6

reserved

INTAUX

auxiliary interrupt line

4 to 0

INT[4:0][1]

These interrupt bits remain at logic 1 until the interrupt SUPL,

PROT, MUTE and EARLY bits have been read

INT5: card slot 5 interrupt:

set to logic 1: when any of the bits SUPL, PROT, MUTE and

EARLY are set to logic 1

set to logic 0: when any of the bits SUPL, PROT, MUTE and

EARLY are set to logic 0 when read

INT4: card slot 4 interrupt:

set to logic 1: when any of the bits SUPL, PROT, MUTE and

EARLY are set to logic 1

set to logic 0: when any of the bits SUPL, PROT, MUTE and

EARLY are set to logic 0 when read

INT3: card slot 3 interrupt:

set to logic 1: when any of the bits SUPL, PROT, MUTE and

EARLY are set to logic 1

set to logic 0: when any of the bits SUPL, PROT, MUTE and

EARLY are set to logic 0 when read

INT2: card slot 2 interrupt:

set to logic 1: when any of the bits PRESL, SUPL, PROT, MUTE

and EARLY are set to logic 1

set to logic 0: when any of the bits PRESL, SUPL, PROT, MUTE

and EARLY are set to logic 0 when read

INT1: card slot 1 interrupt:

set to logic 1: when any of the bits PRESL, SUPL, PROT, MUTE

and EARLY are set to logic 1

set to logic 0: when any of the bits PRESL, SUPL, PROT, MUTE

and EARLY are set to logic 0 when read

Table 37.

Bank 1 Slew rate register (address 40h; CSb[7:0] = 06h) read/write mode bit

descriptions

Bit

Symbol

Description

7 to 6

CLK_SR[3:2]

card slot 2 to 5 clock slew rate selection

5 to 4

IO_SR[3:2]

card slot 2 to 5 I/O slew rate selection

3 to 2

CLK_SR[1:0]

card slot 1 clock slew rate selection

1 to 0

IO_SR[1:0]

card slot 1 I/O slew rate selection

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