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TDA8026ET/C2 bảng dữ liệu(PDF) 2 Page - NXP Semiconductors |
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TDA8026ET/C2 bảng dữ liệu(HTML) 2 Page - NXP Semiconductors |
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2 / 61 page ![]() TDA8026_1 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. Product data sheet Rev. 1.1 — 30 June 2016 2 of 61 NXP Semiconductors TDA8026 Multiple smart card slot interface IC RST(n) signal lines with current limitation at 20 mA, controlled by an embedded programmable clock pulse counter on asynchronous cards or by a register on synchronous cards ISO 7816-3 and EMV 4.31 payment systems compatibility VDD(INTF) supply voltage supervisor ensures correct communication between microcontroller and circuit; threshold internally fixed or set using an external resistor bridge VDD supply voltage supervisor for spike suppression during power-on and emergency deactivation at power-off; threshold internally fixed Card presence input with a 17.8 ms (typical) built-in debouncing system on card slots 1 and 2 One interrupt signal (IRQN) 3. Applications Point Of Sale terminals Multiple SAM contact readers 4. Quick reference data 1. for C3 version Table 1. Quick reference data VDD = VDD(INTF) = 3.3 V; fclk(ext) = 10 MHz; GND = 0 V; inductor = 10 H; decoupling capacitors on pins VDD and VUP = 10 F; Tamb = 25 C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supply VDD supply voltage on pin VDD; DC-to-DC converter on [1] 2.7 - 5.5 V on pin VDD; DC-to-DC converter off and VCC(n) pin = 5 V [1] 5.25 - 5.5 V IDD supply current shutdown mode - 25 40 A Standby mode - 300 450 A clock-stop mode; all card slots in this mode; fclk(ext) stopped on pins CLK(n); pins CLKIN1 and CLKIN2 either stopped, HIGH-level or LOW-level - 3.7 - mA active mode; all VCC(n) pins = 5 V; fclk(ext) on pins CLK(n) = 5 MHz; ICC(1) = ICC(2) = 55 mA; ICC(3) = ICC(4) = ICC(5) = 2 mA [2] [3] - 210 260 mA VDD(INTF) interface supply voltage on pin VDD(INTF) 1.6 - 3.6 V IDD(INTF) interface supply current shutdown mode - 10 15 A active mode; all VCC(n) pins = 5 V; fclk(ext) on pins CLK(n) = 5 MHz - 35 - A |
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