Antialias

LPF

BCK

Reference

Delta-Sigma

Modulator

1 / 64

Decimation

Filter

With

High-Pass

Filter

Power Supply

AGND

DGND

Clock and Timing Control

LRCK

DOUT

SCKI

Serial

Interface

Mode/

Format

Control

FMT

MD1

MD0

Antialias

LPF

Delta-Sigma

Modulator

1

V L

IN

V

REF

V R

IN

V

CC

V

DD

PCM1808

SLES177B – APRIL 2006 – REVISED AUGUST 2015

www.ti.com

7 Detailed Description

7.1 Overview

The PCM1808 is high-performance, low-cost, single-chip, stereo analog-to-digital converter with single-ended

analog voltage input. The PCM1808 uses a delta-sigma modulator with 64-times oversampling and includes a

digital decimation filter and high-pass filter that removes the dc component of the input signal. For various

applications, the PCM1808 supports master and slave mode and two data formats in serial audio interface up to

96-kHz sampling. These features are controlled through hardware by pulling pins high or low with resistors or a

controller GPIO. The PCM1808 also supports a power-down and reset function by means of halting the system

clock.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Hardware Control

Pins FMT, MD0, and MD1 allow the device to be controlled by either pullup or pulldown resistors as well as

GPIO from a digital IC. These controls allow the option of switching between I2S or left-justified, and in which

interface mode the device operates.

7.3.2 System Clock

The PCM1808 device supports 256 fS, 384 fS, and 512 fS as system clock, where fS is the audio sampling

frequency. The system clock input must be on SCKI (pin 6).

The PCM1808 device has a system-clock detection circuit which automatically senses if the system-clock

operation is at 256 fS, 384 fS, or 512 fS in slave mode. In master mode, control of the system clock frequency

must be through the serial control port, which uses MD1 (pin 11) and MD0 (pin 10). An internal circuit

automatically divides down the system clock to generate frequencies of 128 fS and 64 fS, which operate the

digital filter and the delta-sigma modulator, respectively.

Table 1 shows some typical relationships between sampling frequency and system clock frequency, and Figure 1

shows system clock timing.

Table 1. Sampling Frequency and System Clock Frequency

SAMPLING FREQUENCY (kHz)

SYSTEM CLOCK FREQUENCY (fSCLK) (MHz)

256 fS

384 fS

512 fS

8

2.048

3.072

4.096

16

4.096

6.144

8.192

32

8.192

12.288

16.384

44.1

11.2896

16.9344

22.5792

14

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