PCM1808

SLES177B – APRIL 2006 – REVISED AUGUST 2015

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7.3.4 Power On

The PCM1808 device has an internal power-on-reset circuit, and initialization (reset) occurs automatically when

the power supply (VDD) exceeds 2.2 V (typical). While VDD < 2.2 V (typical), and for 1024 system-clock counts

after VDD > 2.2 V (typical), the PCM1808 device stays in the reset state and the digital output remains zero. After

release of the reset state, 8960 / fS seconds must pass before the digital output becomes valid. Because of the

performing of the fade-in operation, it takes additional time of 48 / fin or 48 / fS to obtain the data corresponding to

the analog input signal. Figure 2 illustrates the power-on timing and the digital output.

7.3.5 Serial Audio Data Interface

The PCM1808 device interfaces the audio system through LRCK (pin 7), BCK (pin 8), and DOUT (pin 9).

7.3.5.1 Interface Mode

MD1 (pin 11) and MD0 (pin 10) select master mode and slave mode as interface modes, both of which the

PCM1808 device supports.Table 2 shows the interface-mode selections. It is necessary to set MD1 and MD0

prior to power on.

In master mode, the PCM1808 device provides the timing of serial audio data communications between the

PCM1808 device and the digital audio processor or external circuit. While in slave mode, the PCM1808 device

receives the timing for data transfer from an external controller.

Table 2. Interface Modes

MD1 (PIN 11)

MD0 (PIN 10)

INTERFACE MODE

Low

Low

Slave mode (256 fS, 384 fS, 512 fS autodetection)

Low

High

Master mode (512 fS)

High

Low

Master mode (384 fS)

High

High

Master mode (256 fS)

7.3.5.1.1

Master Mode

In master mode, BCK and LRCK work as output pins, timing which from the clock circuit of the PCM1808 device

controls these pins. The frequency of BCK is constant at 64 BCK/frame.

7.3.5.1.2

Slave Mode

In slave mode, BCK and LRCK work as input pins. The PCM1808 device accepts 64-BCK/frame or 48-

BCK/frame format (only for a 384-fS system clock), not 32-BCK/frame format.

7.3.5.2 Data Format

Table 3. Data Format

FORMAT NO.

FMT (Pin 12)

FORMAT

0

Low

I2S, 24-bit

1

High

Left-justified, 24-bit

16

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