LAN9252SLASHML datasheet(244/329 Pages) MICROCHIP

244 / 329 page

LAN9252

DS00001909A-page 244

 2015 Microchip Technology Inc.

12.14.26 ASIC CONFIGURATION REGISTER

Note 12:

The default value of this field can be configured via EEPROM. Refer to Section 12.8, "EEPROM Configu-

rable Registers," on page 201 for additional information.

Note:

For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the

highest address.

12.14.27 RESERVED REGISTER

Note 13:

The default value of this field can be configured via EEPROM. Refer to Section 12.8, "EEPROM Configu-

rable Registers," on page 201 for additional information.

Note:

For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the

highest address.

Offset:

0142h-0143h

Size:

16 bits

Bits

Description

ECAT

Type

PDI

Type

Default

MI Link Detection

(Link configuration, link detection, registers PHY Port Status

Registers)

Not available

MI Link Detection Active

Note 12

14:6

RESERVED

0000000b

Note 12

MI Write Gigabit Register 9 Enable

Enables writes to PHY register 9 for PHYs which use this regis-

ter per IEEE 802.3

MI writes to Gigabit register 9 disabled

MI writes to Gigabit register 9 enabled

Note 12

6:0

RESERVED

0000000b

Note 12

Offset:

0144h-0145h

Size:

16 bits

Bits

Description

ECAT

Type

PDI

Type

Default

15:0

RESERVED

0000h

Note 13

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