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LAN9252/ML bảng dữ liệu(PDF) 240 Page - Microchip Technology

tên linh kiện LAN9252/ML
Giải thích chi tiết về linh kiện  2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs
PDF  329 Pages
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nhà sản xuất  MICROCHIP [Microchip Technology]
Trang chủ  http://www.microchip.com
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LAN9252
DS00001909A-page 240
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12.14.21 AL STATUS REGISTER
Note 9:
This register is only writable if Device Emulation is off (Device Emulation bit of ESC Configuration Register
is 0). Otherwise, this register will reflect the AL Control Register values. Reading this register from ECAT
clears the AL Status Event bit in the ECAT Event Request Register.
Note:
For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the
highest address.
12.14.22 AL STATUS CODE REGISTER
Offset:
0130h-0131h
Size:
16 bits
Bits
Description
ECAT
Type
PDI
Type
Default
15:5
RESERVED
Write as 0.
RO
R/W
Note 9
000h
4
Error Ind
0:
Device is in state as requested or Flag cleared by command
1:
Device has not entered requested state or changed state as a
result of a local action
RO
R/W
Note 9
0b
3:0
Actual State of the Device State Machine
1h:
Init State
2h:
Pre-Operational State
3h:
Bootstrap State
4h:
Safe-Operational State
8h:
Operational State
RO
R/W
Note 9
1h
Offset:
0134h-0135h
Size:
16 bits
Bits
Description
ECAT
Type
PDI
Type
Default
15:0
AL Status Code
RO
R/W
0000h
Note:
For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the
highest address.



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