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LAN9252/ML bảng dữ liệu(PDF) 91 Page - Microchip Technology

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LAN9252/ML bảng dữ liệu(HTML) 91 Page - Microchip Technology

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 2015 Microchip Technology Inc.
DS00001909A-page 91
LAN9252
16-BIT READ AND WRITE
For writes, the address is set to access the lower WORD of the Configuration Register. Data on D[15:0] is written on the
trailing edge of WR. The cycle repeats for the upper WORD of the Configuration Register, if desired by the host.
For reads, the address is set to access the lower WORD of the Configuration Register. Read data is driven on D[15:0]
during RD active. The cycle repeats for the upper WORD of the Configuration Register, if desired by the host.
8-BIT READ AND WRITE
For writes, the address is set to access the lower BYTE of the Configuration Register. Data on D[7:0] is written on the
trailing edge of WR. D[15:8] pins are not used or driven. The cycle repeats for the remaining BYTEs of the Configuration
Register, if desired by the host.
For reads, the address is set to access the lower BYTE of the Configuration Register. Read data is driven on D[7:0]
during RD active. D[15:8] pins are not used or driven. The cycle repeats for the remaining BYTEs of the Configuration
Register, if desired by the host.
FIGURE 9-25:
INDEXED ADDRESSING CONFIGURATION REGISTER ACCESS - 16-BIT WRITE/
READ
FIGURE 9-26:
INDEXED ADDRESSING CONFIGURATION REGISTER ACCESS - 8-BIT WRITE/
READ
CS
RD
WR
CONFIG,1'b0
Data 15:8
D[15:8]
A[4:1]
CONFIG,1'b1
Data 31:24
Data 7:0
D[7:0]
Data 23:16
CONFIG,1'b0
Data 15:8
Data 7:0
CONFIG,1'b1
Data 31:24
Data 23:26
CS
RD
WR
CONFIG,2'b00
D[15:8]
A[4:0]
CONFIG,2'b01
Data 7:0
D[7:0]
Data 15:8
CONFIG,2'b00
CONFIG,2'b01
CONFIG,2'b10
CONFIG,2'b11
Data 23:16
Data 31:24
Hi-Z
Data 7:0
Data 15:8
Data 23:16
Data 31:24
CONFIG,2'b10
CONFIG,2'b11



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