TDA7546 datasheet(28/68 Pages) STMICROELECTRONICS

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Functional description

TDA7546

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factor (IDF), output divider factor (ODF), multiplication factor (MF) and fractional factor

(FRA) must be found (max. fsys tolerance ±0.7KHz). For fractional mode an additional

dither can be enabled (DITEN) to eliminate tones in the PLL output clock. The fractional

mode can be disabled (FRAEN) if not needed.

The system clock (fsys) is equal to the XTI input clock after reset. After the PLL is locked,

the system clock will switch automatically to the PLL output clock. Then the SPI/I2C can be

used at the maximum speed of 400kbits/s.

The initialization of the PLL must be done only once after hardware reset. After PLL locking

the RDS functionality can be used regardless of the PLL.

It is possible to disabled all clock for power down mode, which can be external hardware

reset .

5.2.3

Sigma delta converter

The sigma delta modulator is a 3rd order (second order-first order cascade) structure.

Therefore a multi bit output (2 bit streams) represents the analog input signal. A next digital

noise canceller will take the 2 bit streams and calculates a combined stream which is then

fed to the decimation filter. The modulator works at a sampling frequency of fsys/2. The over

sampling factor in relation to the band of interest (57KHz ± 2.4KHz) is 38.

5.2.4

Demodulator

The demodulator includes:

–

RDS quality indicator with selectable sensitivity

–

Selectable time constant of 57KHz PLL

–

Selectable time constant of bit PLL

–

Time constant selection done automatically or by software

The demodulator is fed by the 57KHz bandpass filter and interpolated multiplex signal. The

input signal passes a digital filter extracting the sinus and cosinus components, to be used

for further processing.

The sign of both channels are used as input for the ARI indicator and for the 57KHz PLL.

A fast ARI indicator determines the presence of an ARI carrier. If an ARI carrier is present,

the 57KHz PLL is operating as a normal PLL, else it is operating as a Costas loop.

One part of the PLL is compensating the integral offset (frequency deviation between

oscillator and input signal).

One channel of the filter is fed into the half wave integrator. Two half waves are created, with

a phase deviation of 90 degrees. One wave represents the RDS component, whereas the

other wave represents the ARI component.

The sign of both waves are used as reference for the bit PLL (1187.5 Hz).

The RDS wave is then fed into the half wave extractor. This leads into an RDS signal, which

after integration and differential decoding represents the RDS data.

In a similar way a quality bit can be calculated. This is useful to optimize error correction.

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