TDA7546 datasheet(60/68 Pages) STMICROELECTRONICS

60 / 68 page

Software specifications

TDA7546

60/68

rds_bd_h and rds_bd_l without interruption. This must be done until the “bne” bit is set

to zero (last RDS block).

If the SPI master is not able to handle the above protocol, it must read always at least

the first five registers rds_int, rds_qu, rds_corrp, rds_bd_h, rds_bd_l out independent if

“bne” is set or not. If the “bne” flag is set the whole RAM Buffer must be read out, by

reading each time at least the five registers rds_int, rds_qu, rds_corrp, rds_bd_h and

rds_bd_l without interruption. This must be done until the “bne” bit is set to zero (last

RDS block).

Note:

In polling mode the interrupt flag “int” is just a indication that the wanted information is stored

within the RAM buffer.

Note:

In polling mode it is possible that the last RDS data (rds_qu, rds_corrp, rds_bd_h and

rds_bd_l), which was read out as the “bne” flag was set to zero, is identical to the RDS data

before. This must be checked by the external micro controller by comparing the last received

2 RDS blocks. If they are identical, one of them can be skipped (This is the case if just one

RDS block is stored within the RAM buffer).

Hereafter you can find typical read/write access in SPI mode:

Figure 19.

Write rds_int, rds_bd_ctrl and pll_reg4 registers in SPI mode, reading

RDS data and related flags

Figure 20.

Read out RDS data and related flags, no update of rds_int and

rds_bd_ctrl registers

Note:

sinc4reg and testreg must be zero filled for application.

CSN

DATAIN

DATAOUT

CLK

rds_int[0]

rds_int[1]

rds_int[7]

testreg[0]

rds_int[6]

rds_int[0]

rds_int[1]

rds_int[2]

rds_int[3]

rds_int[4]

rds_int[5]

testreg[1]

shift of DATAIN

in shiftregister

update of

shiftregister with

registers content

update of registers

with shiftregister

content if requested

tcsu

tsu

todv toh

tcsh

tcl tch

CSN

DATAIN

DATAOUT

CLK

rds_int[7:0]

rds_qu[7:0]

rds_corrp[7:0]

rds_bd_h[7:0]

rds_bd_l[7:0]

{0,x,x,x,x,x,x,x}

{x,x,x,x,x,x,x,x}

testreg[7:0]

sinc4reg[7:0]

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