TDA7546 datasheet(55/68 Pages) STMICROELECTRONICS

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TDA7546

Software specifications

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Table 48.

pllreg1 register

Table 49.

pllreg0 register

Note:

sinc4reg and testreg registers are dedicated for testing and are not described in this

specification.

Reset values of rds_qu, rds_corrp, rds_bd_h and rds_bd_l registers are not visible for the

programmer, because he can see only the copy of this registers in the RAM buffer after a

new RDS block was received.

The pllreg4-0 registers must be initialized first, before the RDS functionality can be used. If

the “PLLEN” bit of pllreg4 is set from zero to one, then the PLL will be initialized after

I2C/SPI transfer with the actual values of pllreg4-0. After the lock time the PLL switches

automatically over to the PLL output clock. The next I2C/SPI transfer is only allowed after the

lock time (500

μs) and additional 25 XTI input clock cycles. If the “PLLEN” bit is set from one

to zero, the PLL will be stopped and the system clock is switched back to the XTI input clock

(after the I2C/SPI transfer). The next I2C/SPI transfer is then only allowed after 25 XTI input

clock cycles. This is to avoid any I2C/SPI communication during clock switching.

The registers pllreg3-1 can be only changed at once. If there are less then all three pllreg3-

1 registers written during a I2C/SPI transfer, then they will be not updated.

If the XTI input frequency is 10.25MHz, then only register pllreg4 must be programmed,

because the pllreg3-0 register reset values can be used without any modification.

(10) Reset values are designed for 10.25 MHz XTI in-

put frequency.

(11) MF values smaller than 9 are ignored, 9 is then

used internally.

bit 8 of fractional factor (10) (12).

bit 9 of fractional factor (10) (12).

bit 10 of fractional factor (10) (12).

bit 11 of fractional factor (10) (12).

bit 12 of fractional factor (10) (12).

bit 13 of fractional factor (10) (12).

bit 0 of PLL multiplication factor (10) (11) (12).

bit 1 of PLL multiplication factor (10) (11) (12).

bit name

access

bit 7

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

r/w

FRA8

FRA9

FRA12

MF1

FRA13

MF0

FRA11 FRA10

reset value

pllreg1

(12) The registers pllreg3, pllreg2 and pllreg1 must be

written at once to be updated, i.e. if the I2C/SPI stops

after pllreg2, then these registers are not updated.

bit 0 of fractional factor (10).

bit 1 of fractional factor (10).

bit 2 of fractional factor (10)

bit 3 of fractional factor (10).

bit 4 of fractional factor (10).

bit 5 of fractional factor (10).

bit 6 of fractional factor (10).

bit 7 of fractional factor (10).

bit name

access

bit 7

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

r/w

FRA0

FRA1

FRA4

FRA7

FRA5

FRA6

FRA3

FRA2

reset value

000

pllreg0

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