3.2

March 26, 2021

ES9016K2M Datasheet

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-

8800 • www.esstech.com

18

Register #12: DPLL/ASRC Settings

8 bit, Read-Write Register, Default = 0x5A

Bits

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

Mnemonic

dpll_bw_i2s

dpll_bw_dsd

Default

0

1

0

1

1

0

1

0

Bit

Mnemonic

Description

[7:4]

dpll_bw_i2s

DPLL bandwidth setting for I2S and SPDIF modes (16 settings)

4’b0000 : OFF

4’b0001 : Lowest Bandwidth

4’b0101 : (default)

4’b1010 :

4’b1111 : Highest Bandwidth

[3:0]

dpll_bw_dsd

DPLL bandwidth setting for DSD mode (16 settings)

4’b0000 : OFF

4’b0001 : Lowest Bandwidth

4’b0101 :

4’b1010 : (default)

4’b1111 : Highest Bandwidth

Register #13: THD Compensation

8 bit, Read-Write Register, Default = 0x40

Bits

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

Mnemonic

reserved *

bypass_thd

reserved *

Default

0

1

0

0

0

0

0

0

Bit

Mnemonic

Description

[7]

reserved *

[6]

bypass_thd

1’b0: enable THD compensation

•

output = input + (input2) x thd_comp_c2 + (input3) x thd_comp_c3

•

thd_comp_c2 is stored in registers 23-22 (16 bits signed) (register 23 stores MSBs)

•

thd_comp_c3 is stored in registers 25-24 (16 bits signed) (register 25 stores MSBs)

1’b1: disable THD compensation (default)

•

PCM mode: output = input; DSD mode: output = input / 2

[5:0]

reserved

* All Reserved Bits in Register #13 must be set to the indicated logic level to ensure correct device operation.

THD compensation can be used to reduce the 2nd and 3rd harmonic distortion introduced by external output drivers.

A system level tuning is required to arrive at the optimum coefficients for thd_comp_c2 and thd_comp_c3.

Notes:

•

To get the same gain (output = input) for PCM and DSD modes without THD compensation, bypass_thd should be set to

1’b0 with thd_comp_c2 and thd_comp_c3 set to 16’d0 (default)

•

Erroneous compensation can lead to higher distortion than the one without compensation. If accurate tuning cannot be

performed, thd_comp_c2 and thd_comp_c3 should be set to 16’d0 (default) if bypass_thd is set to 1’b0.