3.2

March 26, 2021

ES9016K2M Datasheet

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-

8800 • www.esstech.com

16

Register #10: Master Mode Control

8 bit, Read-Write Register, Default = 0x5

Bits

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

Mnemonic

master_clock_enable

clock_divider_select

sync_mode

stop_div

Default

0

0

0

0

0

1

0

1

Bit

Mnemonic

Description

[7]

master_clock_enable

1'b0 disables master mode (default)

1'b1 enables master mode (driving Bit clock and Frame Clock)

[6:5]

clock_divider_select

2'b00: Bit Clock frequency = MCLK / 4 (default)

2'b01: Bit Clock frequency = MCLK / 8

2b10: Bit Clock frequency = MCLK / 16

2'b11: Bit Clock frequency = MCLK / 16

Frame Clock frequency = Bit Clock frequency / 64

[4]

sync_mode

1'b1 to enable quick lock if the fs and MCLK are synchronous and MCLK is 128 x FSR.

1'b0 for normal operation of the DPLL and ASRC.

Note: quick lock can only be used in PCM normal mode.

[3:0]

stop_div

Sets the number of FSR edges that must occur before the DPLL and

ASRC can lock on to the incoming signal.

4'd0 = 16384 FSR edges

4'd1 = 8192 FSR edges

4'd2 = 5461 FSR edges

4'd3 = 4096 FSR edges

4'd4 = 3276 FSR edges

4'd5 = 2730 FSR edges (default)

4'd6 = 2340 FSR edges

4'd7 = 2048 FSR edges

4'd8 = 1820 FSR edges

4'd9 = 1638 FSR edges

4'd10 = 1489 FSR edges

4'd11 = 1365 FSR edges

4'd12 = 1260 FSR edges

4'd13 = 1170 FSR edges

4'd14 = 1092 FSR edges

4'd15 = 1024 FSR edges

For correct operation, master mode

should only be enabled when the DAC’s input mode is set to I2S, and when i2s_length is

set to 32-bit and i2s_mode is set to I2S in register 1.

When master mode is enabled, the DATA_CLK pin will output Bit Clock and the DATA1 pin will output Frame Clock at

frequencies specified by clock divider select.

For compatibility with Rev. W, or when PCM data with FSR >

96kHz is used, stop_div should be set to 4’d0 (16384 FSR

edges).