PCA2129TSLASHQ900SLASH2 datasheet(56/84 Pages) NXP

56 / 84 page

PCA2129

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Product data sheet

Rev. 5 — 19 December 2014

56 of 84

NXP Semiconductors

PCA2129

Automotive accurate RTC with integrated quartz crystal

The R/W bit defines the direction of the following single or multiple byte data transfer (read

is logic 1, write is logic 0).

For the format and the timing of the START condition (S), the STOP condition (P), and the

acknowledge (A) refer to the I2C-bus specification Ref. 13 “UM10204” and the

characteristics table (Table 82). In the write mode, a data transfer is terminated by sending

a STOP condition. A repeated START (Sr) condition is not applicable.

9.3 Bus communication and battery backup operation

To save power during battery backup operation (see Section 8.5.1), the bus interfaces are

inactive. Therefore the communication via I2C- or SPI-bus should be terminated before

the supply of the PCA2129 is switched from VDD to VBAT.

Remark: If the I2C-bus communication was terminated uncontrolled, the I2C-bus has to

be reinitialized by sending a STOP followed by a START after the device switched back

from battery backup operation to VDD supply operation.

Table 77.

I2C slave address byte

Slave address

Bit

MSB

LSB

1R/W

Fig 36. Bus protocol, writing to registers

Fig 37. Bus protocol, reading from registers

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