13892 datasheet(69/158 Pages) FREESCALE

69 / 158 page

FUNCTIONAL DEVICE OPERATION

OPERATING MODES

Analog Integrated Circuit Device Data



Freescale Semiconductor

MC13892

POWER GATING SPECIFICATIONS AND CONTROL

A power gate driver pulled low may be thought of as power gating being active since this is the condition where a power source

is isolated (or power gated) from its loading on the other side of the switch. The power gate drive outputs are SPI controlled in

the active modes as shown in Table 38.

When SPI controlled (Watchdog, On, and User Off Wait states), the PWGTDRVx power gate drive pin states are determined

by SPI enable bits PWGTxSPIEN, according to Table 39.

GENERAL PURPOSE OUTPUTS

GPO drivers included can provide useful system level signaling with SPI enabling and programmable Standby control. Key

use cases for GPO outputs include battery pack thermistor biasing and enabling of peripheral devices, such as light sensor(s),

camera flash, or even supplemental regulators.

SPI enabling can be used for coordinating GPOs with ADC conversions for consumption efficiency and desired settling

characteristics.

Four general purpose outputs are provided, summarized in Table 40 and Table 41 (active high polarities assumed).

Table 37. Power Gating Characteristics

Parameter

Condition

Min

Typ

Max

Units

Output Voltage VOUT

Output High

5.0

5.40

5.70

Output Low

–

100

Turn-on Time (66), (67)

Enable to VOUT = VOUTMIN -250 mV

–

100

s

Turn Off Time

Disable to VOUT < 1.0 V

–

1.0

s

Average Bias Current

t > 500

s after Enable

–

1.0

5.0

A

PWGTx Input Voltage

NMOS drain voltage

0.6

–

2.0

DC Load Current

At PWGTDRVx output

–

100

Load Capacitance (66)

Used as a condition for the other parameters

0.5

–

1.0

Notes

66.

Larger capacitive loading values will lead to longer turn on times exceeding the given limits; smaller values will lead to larger ripple at

the output.

67.

Input supply is assumed in the range of 3.0 < BP < 4.65 V; lower BP values may extend turn on time, and functionality not supported

for BP less than ~2.7 V.

Table 38. Power Gate Drive State Control

Mode

PWGTDRV1

PWGTDRV2

Off

Low

Cold Start

Low

Warm Start

Low

Watchdog, On, User Off Wait

SPI Controlled

User Off, Memory Hold, Internal Memory Hold Power Cut

Low

Table 39. Power Gating Logic Table

PWGTxSPIEN

PWGTDRVx

Low

High

Notes

68.

Applicable for Watchdog, On and User Off Wait modes only. If PWGT1SPIEN

AND PWGT2SPIEN both = 1 then the charge pump is disabled.

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