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TMP86FS28DFG bảng dữ liệu(PDF) 65 Page - Toshiba Semiconductor

tên linh kiện TMP86FS28DFG
Giải thích chi tiết về linh kiện  8 Bit Microcontroller
PDF  272 Pages
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nhà sản xuất  TOSHIBA [Toshiba Semiconductor]
Trang chủ  http://www.semicon.toshiba.co.jp/eng
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TMP86FS28DFG bảng dữ liệu(HTML) 65 Page - Toshiba Semiconductor

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TMP86FS28DFG
5.1 Port P0 (P00 to P02)
Port P0 is a 3-bit input/output port that can also be used for external interrupt input or PPG output.
A reset initializes the output latch (P0DR) to “1” and the Pch control (P0OUTCR) to “0”.
To use a pin in Port P0 as an input port or external interrupt input, set P0DR to “1” and then set the corresponding
bit in P0OUTCR to “0”.
To use a pin in Port P0 as a PPG output, set P0DR to “1”.
The output circuit of Port P0 can be set either as sink open-drain output (“0”) or CMOS output (“1”) individually
for each bit in P0OUTCR.
Port P0 has a separate data input register. The output latch state can be read from the P0DR register, and the pin
state can be read from the P0PRD register.
Figure 5-2 Port P0
Table 5-3 Register Programming for Port P0 (P00 to P02)
Function
Programmed Value
P0DR
P0OUTCR
Port input, external interrupt input
“1”
“0”
Port "0" output
“0”
Set as
appropriate.
Port "1" output, PPG output
“1”
Data input (P0PRD)
Output latch read (P0DR)
STOP
OUTEN
P0OUTCRi input
Data output (P0DR)
P0OUTCRi
P0i
Note) i = 2~0
DQ
DQ
Control output
Control input
Output latch



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