TMP86FS23UG datasheet(195/252 Pages) TOSHIBA

195 / 252 page

Page 183

TMP86FS23UG

17.6.1 Operation Status Flag (CALC)

CALC indicates the status of the MAC unit. It is set to "1" when calculation is in progress and "0" when cal-

culation is not in progress.

17.6.2 Overflow Flag (OVRF)

OVRF is set to “1” if the sum of positive values is negative or the sum of negative values is positive in signed

multiply-accumulate mode. In other cases, it is cleared to “0”.

Note:In multiply mode, OVRF is always read as "0".

17.6.3 Carry Flag (CARF)

CARF is set to “1” if a carry occurs in the highest-order bit (bit 31) in a multiply-accumulate operation. In

other cases, it is cleared to "0".

Note: In multiply mode, CARF is always read as "0".

17.6.4 Sign Flag (SIGN)

SIGN contains the same data as the highest-order bit (bit 31) of the calculation result (regardless of whether

calculation is performed in signed or unsigned mode).

Note:SIGN is programmed by the calculation result. This flag is not affected by a write to the addend register.

17.6.5 Zero Flag (ZERF)

ZERF is set to “1” if the result register contains “00000000H”. In other cases, it is cleared to “0”. It is also set

to “1” if the result register contains “00000000H” after an overflow or carry has occurred.

Note:ZERF is programmed by the calculation result. This flag is not affected by a write to the addend register.

17.7 Example of Software Processing

The following shows an example of calculating X =

αx + βy + γz. The calculation time is 3µs when fc = 8 MHz.

The multiplier and multiplicand are separately stored in data RAM. The W and A registers are used as general-pur-

pose registers. The general-purpose registers are not saved on the stack. The processing for enabling/disabling the

MAC unit is not included.

Note 1: If the operation mode is changed by processing an interrupt during calculation, the correct calculation result may

not be obtained. Thus, before starting calculation, be sure to execute the DI instruction to disable interrupts.

Note 2: Before reading the result register after calculation is started, check that the CALC flag in the MACSR register is

"0" or wait for at least three machine cycles (e.g. NOP x 3).

Instruction

Processing Time

(Disables interrupts.)

WA, (RAM_Multiplier

α)

6 cycles/3

µs

(MPLDRL), WA

; Multiplier register

6 cycles/3

µs

WA, (RAM_Multiplier x)

6 cycles/3

µs

(MPCDRL), WA

; Multiplicand register

6 cycles/3

µs

; The next data can be

written in succession.

TMP86FS23UG bảng dữ liệu(PDF) 195 Page - Toshiba Semiconductor

TMP86FS23UG bảng dữ liệu(HTML) 195 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL