TMP86FS23UG datasheet(95/252 Pages) TOSHIBA

95 / 252 page

Page 83

TMP86FS23UG

8.3 Function

TC1 has four operating modes. The timer mode of the TC1 is used at warm-up when switching form SLOW mode

to NORMAL2 mode.

8.3.1 Timer mode

In this mode, counting up is performed using the internal clock. The contents of TREGIA are compared with

the contents of up-counter. If a match is found, an INTTC1 interrupt is generated, and the counter is cleared.

Counting up resumes after the counter is cleared.

Note: When fc is selected for the source clock in SLOW mode, the lower bits 11 of TREG1A is invalid, and a match of the upper

bits 7 makes interrupts.

TC1 status register

TC1SR

(0016H)

3210

HECF

HEOVF

"0"

(Initial value: 0000 0000)

HECF

Operating Status monitor

Stop (during Tb) or disable

Under counting (during Ta)

Read

only

HEOVF

Counter overflow monitor

No overflow

Overflow status

Table 8-1 Source clock (internal clock) of Timer/Counter 1

Source Clock

Resolution

Maximum Time Setting

NORMAL1/2, IDLE1/2 Mode

SLOW Mode

SLEEP Mode

fc = 16 MHz

fs =32.768

kHz

fc = 16 MHz

fs =32.768

kHz

DV7CK = 0

DV7CK = 1

fc/223 [Hz]

fs/215 [Hz]

0.52 s

1 s

38.2 h

72.8 h

fc/213

fs/25

512 ms

0.98 ms

2.2 min

4.3 min

fc/211

fs/23

128 ms

244 ms

0.6 min

1.07 min

fc/27

8 ms

2.1 s

fc/23

0.5 ms

131.1 ms

fc (Note)

62.5 ns

16.4 ms

30.5 ms

8 s

TMP86FS23UG bảng dữ liệu(PDF) 95 Page - Toshiba Semiconductor

TMP86FS23UG bảng dữ liệu(HTML) 95 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL