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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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TMP88CS43FG bảng dữ liệu(PDF) 98 Page - Toshiba Semiconductor |
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TMP88CS43FG bảng dữ liệu(HTML) 98 Page - Toshiba Semiconductor |
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98 / 218 page  Page 88 9. 16-Bit Timer (CTC) 9.2 Control TMP88CS43FG 9.3.2 Timer mode with external trigger start In this timer mode, the timer/counter starts counting as triggered by input on CTC pin (rising or falling edge selected with CTC1CR1<CTC1SE>). The source clock is an internal clock. For successive cycles, when the counter value and the set value of the CTC1DRA Register match, an INTCTC1 interrupt is generated and the counter is cleared and then restarted. The counter is stopped by a trigger input on CTC pin and restarted by the next trigger input. For a one-shot cycle, when the counter value and the set value of the CTC1DRA Register match, an INTCTC1 interrupt is generated and the counter is cleared and stopped. The counter restarts count- ing up by input on CTC pin. When CTC1CR1<CTC1E> = 1, the counter is cleared and stops counting at an edge on CTC pin input opposite the active edge that triggers the counter to start counting. In this mode, an interrupt can be generated by entering a pulse which has a certain width. When CTC1CR1<CTC1E> = 0, opposite edges on CTC input are ignored. Figure 9-3 External Trigger Mode Timing Chart 1 2 n - 1 0 22 1 1 n 3 4 CTC pin input Internal clock Counter (I) When rising edge start is selected, with counting enabled on one edge ( CTC1SE = 0, CTC1E = 0 ) Timer Register A Count start Count start Stop INTCTC1 interrupt n Successive Clear Trigger Trigger Trigger 1 2 n - 1 0 36 0 5 n 4 1 2 CTC pin input Internal clock Counter Timer Register A Count start Count start INTCTC1 interrupt n One Shot Stop Trigger Trigger |
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