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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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DSP56321 bảng dữ liệu(PDF) 31 Page - Freescale Semiconductor, Inc |
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DSP56321 bảng dữ liệu(HTML) 31 Page - Freescale Semiconductor, Inc |
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31 / 84 page  AC Electrical Characteristics DSP56321 Technical Data, Rev. 11 Freescale Semiconductor 2-11 2.4.5 External Memory Expansion Port (Port A) 2.4.5.1 SRAM Timing Table 2-8. SRAM Timing No. Characteristics Symbol Expression1 200 MHz 220 MHz 240 MHz 275 MHz Unit Min Max Min Max Min Max Min Max 100 Address valid and AA assertion pulse width2 tRC, tWC (WS + 2) × T C −4.0 [3 ≤WS ≤7] (WS + 3) × TC −4.0 [WS ≥ 8] 21.0 51.0 — 18.8 46.0 — 16.9 41.9 — 15.0 36.0 — ns ns 101 Address and AA valid to WR assertion tAS 0.75 × TC – 3.0 [WS = 3] 1.25 × TC – 3.0 [WS ≥ 4] 0.75 3.25 — — 0.41 2.69 — — 0.13 2.21 — — –0.27 1.54 — — ns ns 102 WR assertion pulse width tWP WS × TC −4.0 [WS = 3] (WS −0.5) × T C −4.0 [WS ≥ 4] 11.0 13.5 — — 9.65 11.93 — — 8.51 10.6 — — 6.9 8.72 — — ns ns 103 WR deassertion to address not valid tWR 1.25 × T C −4.0 [3 ≤WS ≤7] 2.25 × TC −4.0 [WS ≥ 8] 2.25 7.25 — — 1.69 6.24 — — 1.21 5.38 — — 0.54 4.18 — — ns ns 104 Address and AA valid to input data valid tAA, tAC (WS + 0.75) × TC −5.8 [WS ≥ 3] — 12.9 — 11.2 — 9.8 — 7.84 ns 105 RD assertion to input data valid tOE (WS + 0.25) × TC −6.5 [WS ≥ 3] — 9.75 — 8.29 — 7.05 — 5.31 ns 106 RD deassertion to data not valid (data hold time) tOHZ 0.0 — 0.0 — 0.0 — 0.0 — ns 107 Address valid to WR deassertion2 tAW (WS + 0.75) × TC −4.0 [WS ≥ 3] 14.75 — 13.06 — 11.64 — 9.63 — ns 108 Data valid to WR deassertion (data setup time) tDS (tDW)(WS −0.25) × TC −5.4 [WS ≥ 3] 8.35 — 7.11 — 6.07 — 4.6 — ns 109 Data hold time from WR deassertion tDH 1.25 × T C −4.0 [3 ≤WS ≤7] 2.25 × TC −4.0 [WS ≥ 8] 2.25 7.25 — — 1.69 6.23 — — 1.21 5.38 — — 0.54 4.18 — — ns ns 110 WR assertion to data active —0.25 × TC −4.0 [WS = 3] –0.25 × TC −4.0 [WS ≥ 4] –2.75 –5.25 — — –2.86 –5.14 — — –2.96 –5.04 — — –3.1 –4.91 — — ns ns 111 WR deassertion to data high impedance —1.25 × TC 6.25 — 5.69 — 5.21 — 4.55 — ns 112 Previous RD deassertion to data active (write) —2.25 × TC −4.0 7.25 — 6.23 — 5.38 — 4.18 — ns 113 RD deassertion time — 1.75 × TC −3.0 [3 ≤WS ≤7] 2.75 × T C −3.0 [WS ≥ 8] 5.75 10.75 — — 4.96 9.51 — — 4.3 8.47 — — 3.36 7.0 — — ns ns 114 WR deassertion time4 —2.0 × T C −3.0 [3 ≤WS ≤7] 3.0 × TC −3.0 [WS ≥ 8] 7.0 12.0 — — 6.1 10.6 — — 5.3 9.5 — — 4.27 7.91 — — ns ns |
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