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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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DSP56321 bảng dữ liệu(PDF) 27 Page - Freescale Semiconductor, Inc |
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DSP56321 bảng dữ liệu(HTML) 27 Page - Freescale Semiconductor, Inc |
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27 / 84 page  AC Electrical Characteristics DSP56321 Technical Data, Rev. 11 Freescale Semiconductor 2-7 20 Delay from RD assertion to interrupt request deassertion for level sensitive fast interrupts1, 6, 7 (WS + 3.25) × TC – 10.94 — Note 7 — Note 7 — Note 7 — Note 7 ns 21 Delay from WR assertion to interrupt request deassertion for level sensitive fast interrupts1, 6, 7 •SRAM WS = 3 •SRAM WS ≥ 4 (WS + 3) × TC – 10.94 (WS + 2.5) × TC – 10.94 — — Note 7 Note 7 — — Note 7 Note 7 — — Note 7 Note 7 — — Note 7 Note 7 ns ns 24 Duration for IRQA assertion to recover from Stop state 8.0 — 8.0 — 8.0 — 8.0 — ns 25 Delay from IRQA assertion to fetch of first instruction (when exiting Stop)2, 3 • DPLL is not active during Stop (PCTL Bit 1 = 0) and Stop delay is enabled (Operating Mode Register Bit 6 = 0) • DPLL is not active during Stop (PCTL Bit 1 = 0) and Stop delay is not enabled (Operating Mode Register Bit 6 = 1) • DPLL is active during Stop (PCTL Bit 1 = 1; Implies No Stop Delay) DPLT + (128K × TC) DPLT + (23.75 ± 0.5) × TC (10.0 ± 1.75) × TC 662.2 µs 6.9 41.25 209.9 ms 188.8 58.8 662.2 µs 6.9 37.5 209.9 ms 188.8 53.3 662.2 µs 6.9 34.4 209.9 ms 188.8 49.0 662.2 µs 6.9 30.0 209.9 ms 188.8 43.0 — µs ns 26 Duration of level sensitive IRQA assertion to ensure interrupt service (when exiting Stop)2, 3 • DPLL is not active during Stop (PCTL bit 1 = 0) and Stop delay is enabled (Operating Mode Register Bit 6 = 0) • DPLL is not active during Stop (PCTL bit 1 = 0) and Stop delay is not enabled (Operating Mode Register Bit 6 = 1) • DPLL is active during Stop ((PCTL bit 1 = 0; implies no Stop delay) DPLT + (128 K × TC) DPLT + (20.5 ± 0.5) × T C 5.5 × TC 805.4 150.1 27.5 — — — 805.4 150.1 25 — — — 805.4 150.1 22.9 — — — 805.4 150.1 20.0 — — — µs µs ns 27 Interrupt Request Rate • HI08, ESSI, SCI, Timer •DMA •IRQ, NMI (edge trigger) •IRQ, NMI (level trigger) 12TC 8TC 8TC 12TC — — — — 60.0 40.0 40.0 60.0 — — — — 54.6 36.4 36.4 54.6 — — — — 50.0 33.4 33.4 50.0 — — — — 43.7 29.2 29.2 43.7 ns ns ns ns 28 DMA Request Rate • Data read from HI08, ESSI, SCI • Data write to HI08, ESSI, SCI •Timer •IRQ, NMI (edge trigger) 6TC 7TC 2TC 3TC — — — — 30.0 35.0 10.0 15.0 — — — — 27.3 31.9 9.1 13.7 — — — — 25.0 29.2 8.3 12.5 — — — — 21.84 25.48 7.28 10.92 ns ns ns ns 29 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external memory (DMA source) access address out valid 4.25 × TC + 2.0 23.25 — 21.34 — 19.72 — 17.45 — ns Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing5 (CONTINUED) No. Characteristics Expression 200 MHz 220 MHz 240 MHz 275 MHz Unit Min Max Min Max Min Max Min Max |
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