TMP93CS40 datasheet(39/248 Pages) TOSHIBA

39 / 248 page

TMP93CS40/TMP93CS41

2004-02-10

93CS40-37

(SWI3 routine)

(main)

RETI

SWI 3

(main)

INTT0

(Level 3)

INTT1

(Level 4)

(INTT0 interrupt routine)

IFF

←4

IFF

←3

RETI

EI 3

(INTT1 interrupt routine)

IFF

←5

IFF

←4

RETI

(INTT1 interrupt routine)

During processing an interrupt of priority level 3, the IFF is set to

4. When an interrupt with a level higher than 4 is generated, the

CPU accepts the interrupt with the higher priority level, causing

interrupt processing to nest.

The CPU accepts a software interrupt request during DI

status (IFF

= 7) because the request has a priority of level 7.

The IFF is not changed by the software interrupt.

During execution of the main program, the CPU accepts an

interrupt request. The CPU then increments IFF so that no

new interrupts of priority level 1 will be accepted during

processing of the interrupt routine.

The DI instruction is executed in the main program, so that

only interrupts of priority level 7 are accepted. In this state the

CPU does not increment the IFF even if the CPU accepts an

interrupt request of level 7.

If an interrupt with a priority level higher than the interrupt

currently being processed is generated, the CPU accepts the

interrupt with the higher level. The program counter which returns

at [5] is the state address of the INTT0 interrupt routine.

INTT0

(Level 1)

(INTT0 interrupt routine)

(main)

IFF

←2

IFF

←1

RETI

EI 1

(1) Maskable interrupt

NMI

(Level 7)

(NMI routine)

(main)

IFF

←7

IFF

←7

RETI

(2) Non-maskable interrupt

(3) Interrupt nesting

(4) Software interrupt

(main)

(INTT0 interrupt routine)

RETI

EI 3

RETI

INTT1

(Level 4)

XXX

INTT0

(Level 3)

(5) Timing of interrupt acceptance

(underline): Instruction

[1], [2],

…:

Execution flow

[1]

[2]

[3]

[4]

[5]

[1]

[5]

[2]

[3]

[4]

[1]

[5]

[2]

[3]

[4]

[1]

[2]

[3]

[4]

[9]

[8]

[7]

[6]

[5]

[1]

[8]

[2]

[5]

[7]

[4]

[3]

[6]

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