UPSD3422 datasheet(187/293 Pages) STMICROELECTRONICS

187 / 293 page

uPSD34xx

PSD module

187/293

program address space (accessed with PSEN) or XDATA space (accessed with RD or WR)

as defined with PSDsoft Express. The user only has to specify an address range for each

segment, and specify if Secondary Flash memory will reside in 8032 data or program

address space, and then PSEN, RD, or WR are automatically activated for the specified

range. 8032 firmware is easily programmed into Secondary Flash memory using PSDsoft

Express and others. See Table 101 on page 187 for Secondary Flash sector sizes.

28.1.5

SRAM

The SRAM is selected by a single signal, named RS0, from the Decode PLD. SRAM may be

located at any address within 8032 XDATA space (accessed with RD or WR). These choices

are specified using PSDSoft Express, where the user specifies an SRAM address range.

See Table 101 on page 187 for SRAM sizes.

The SRAM may optionally be backed up by an external battery (or other DC source) to

make its contents non-volatile (see Section 28.5.62: SRAM standby mode (battery backup)

on page 250).

Table 101.

uPSD34xx memory configuration

28.1.6

Runtime control registers, csiop

A block of 256 bytes is decoded inside the PSD Module for module control and status (see

Table 106 on page 199). The base address of these 256 locations is referred to in this data

sheet as csiop (Chip Select I/O Port), and is selected by the Decode PLD output signal,

CSIOP. The csiop registers are always viewed by the 8032 as XDATA, and are accessed

with RD and WR signals. The address range of csiop is specified using PSDsoft Express

where the user only has to specify an address range of 256 bytes, and then the RD or WR

signals are automatically activated for the specified range. Individual registers within this

block are accessed with an offset from the specified csiop base address. 39 registers are

used out of the 256 locations to control the output state of I/O pins, to read I/O pins, to set

the memory page, to control 8032 program and data address space, to control power

management, to READ/WRITE macrocells inside the General PLD, and other functions

during runtime. Unused locations within csiop are reserved and should not be accessed.

28.1.7

Memory page register

8032 MCU architecture has an inherent size limit of 64K bytes in either program address

space or XDATA space. Some uPSD34xx devices have much more memory that 64K, so

special logic such as this page register is needed to access the extra memory. This 8-bit

page register (Figure 63) can be loaded and read by the 8032 at runtime as one of the csiop

registers. Page register outputs feed directly into both PLDs creating extended address

Device

Main Flash Memory

Secondary Flash Memory

SRAM

Total

Flash

Size

(bytes)

Individual

Sector

Size

(bytes)

Number of

Sectors

(Sector

Select Signal)

Total

Flash

Size

(bytes)

Individual

Sector

Size

(bytes)

Number of

Sectors

(Sector Select

Signal)

SRAM

Size

(bytes)

uPSD3422

64K

16K

4 (FS0-3)

32K

4 (CSBOOT0-3)

uPSD3433

128K

16K

8 (FS0-7)

32K

4 (CSBOOT0-3)

uPSD3434

256K

32K

8 (FS0-7)

32K

4 (CSBOOT0-3)

uPSD3454

256K

32K

8 (FS0-7)

32K

4 (CSBOOT0-3)

32K

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