UPSD3422 datasheet(79/293 Pages) STMICROELECTRONICS

79 / 293 page

uPSD34xx

MCU bus interface

79/293

A[10:8] and the remaining pins can be configured for other functions such as generating

chip selects to the external devices.

Figure 20.

Connecting external devices using ports A and B for address AD[15:0]

Figure 21.

Connecting external devices using port A and an external latch for

address AD[15:0]

18.4

Programmable bus timing

The length of the bus cycles are user programmable at run time. The number of MCU_CLK

periods in a bus cycle can be specified in the SFR register named BUSCON (see Table 37

on page 81). By default, the BUSCON Register is loaded with long bus cycle times (6

MCU_CLK periods) after a reset condition. It is important that the post-reset initialization

firmware sets the bus cycle times appropriately to get the most performance, according to

Table 38 on page 82. Keep in mind that the PSD Module has a faster Turbo Mode (default)

and a slower but less power consuming Non-Turbo Mode. The bus cycle times must be

programmed in BUSCON to optimize for each mode as shown in Table 38. See

Section 28.5: PSD module detailed operation on page 201 for more details.

uPSD34xx

PSD

Module

External

8-bit

Device

MCU

Module

AI10434

AD[7:0]

D[7:0]

A8-15

A0-7

Port A

Port B

AD[15:8]

PSEN

ALE

RD or WR

uPSD34xx

PSD

Module

External

8-bit

Device

MCU

Module

AI10435

AD[7:0]

D[7:0]

A7-0

A8-15

Port B

AD[15:8]

PSEN

ALE

RD or WR

UPSD3422 bảng dữ liệu(PDF) 79 Page - STMicroelectronics

UPSD3422 bảng dữ liệu(HTML) 79 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL