UPSD3422 datasheet(168/293 Pages) STMICROELECTRONICS

168 / 293 page

USB interface

uPSD34xx

168/293

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USB FIFO Base Address High and Low Registers (UBASEH and UBASEL)

All 10 Endpoint FIFOs share the same 64-byte address range. The 16-bit base

address for the FIFOs is specified using the USB Base Address registers (see Table 85

and Table 86). The USB Endpoint Select Register (see Table 82 on page 165) selects

the direction and the Endpoint for the FIFO that is accessed when addressing the 64-

bytes of XDATA space starting with the base address specified in the Base Address

Registers. The Base Address is a 64-byte segment where the lower 6 bits of the base

Important note: The USB FIFO Base Address must be set to an open 64-byte segment

in the XDATA space. Care should be taken to ensure that there is no overlap of

addresses between the USB FIFOs and the flash memory, SRAM, csiop registers, and

anything else accessed in the XDATA space. While the logic in the PSD module

handles overlap of flash memory, SRAM, and the csiop registers with a fixed priority

(see Section 28.1: PSD module functional description on page 185), this is not the

case with the USB FIFOs. Unpredictable results as well as potential damage to the

device may occur if there is an overlap of addresses.

Table 85.

USB FIFO base address high register (UBASEH 0F3h, reset value 00h)

Table 86.

USB FIFO base address low register (UBASEL 0F4h, reset value 00h)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BASEADDR[15:8]

Bit

Symbol

R/W

Definition

7:0

BASEADDR

[15:8]

R/W

The upper 8 bits of the 16-bit base address for USB FIFOs

to be mapped in XDATA space

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BASEADDR[7:6]

0000

Bit

Symbol

R/W

Definition

7:6

BASEADDR

[7:6]

R/W

Bits 7 and 6 of the 16-bit base address for the USB FIFOs to

be mapped in XDATA space

5:0

BASEADDR

[5:0]

Hardwired '0'

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