UPSD3422 datasheet(155/293 Pages) STMICROELECTRONICS

155 / 293 page

uPSD34xx

USB interface

155/293

Table 70.

USB device address register (UADDR 0E2h, reset value 00h)

Table 71.

Pairing control register (UPAIR 0E3h, reset value 00h)

25.4.3

USB interrupts

There are many USB related events that generate an interrupt. The events that generate an

interrupt are selectively enabled through the use of the USB Interrupt Enable Registers. All

USB interrupts are serviced through a single interrupt vector (see Section 13: Interrupt

system on page 52 for the address of the interrupt vector). When a USB interrupt occurs,

firmware must check the USB Interrupt Flag Registers to determine the source of the

interrupt, clear that interrupt flag and process the interrupt before returning to the interrupted

code.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

–

USBADDR[6:0]

Bit

Symbol

R/W

Definition

–

Reserved

6:0

USBADDR

R/W

USB Address of the device.

These bits are cleared with a Hardware RESET. When a USB

RESET is detected, the address register should be cleared.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

–

PR3OUT

PR1OUT

PR3IN

PR1IN

Bit

Symbol

R/W

Definition

–

Reserved

–

Reserved

–

Reserved

–

Reserved

3PR3OUT

R/W

Setting this bit enables double buffering of the OUT FIFOs for

Endpoints 3 and 4. Access to the double buffered FIFOs is

through Endpoint3’s OUT FIFO.

2PR1OUT

R/W

Setting this bit enables double buffering of the OUT FIFOs for

Endpoints 1 and 2. Access to the double buffered FIFOs is

through Endpoint1’s OUT FIFO.

1PR3IN

R/W

Setting this bit enables double buffering of the IN FIFOs for

Endpoints 3 and 4. Access to the double buffered FIFOs is

through Endpoint3’s IN FIFO.

0PR1IN

R/W

Setting this bit enables double buffering of the IN FIFOs for

Endpoints 1 and 2. Access to the double buffered FIFOs is

through Endpoint1’s IN FIFO.

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