UPSD3422 datasheet(134/293 Pages) STMICROELECTRONICS

134 / 293 page

SPI (synchronous peripheral interface)

uPSD34xx

134/293

SPI (synchronous peripheral interface)

uPSD34xx devices support one serial SPI interface in Master Mode only. This is a three- or

four-wire synchronous communication channel, capable of full-duplex operation on 8-bit

serial data transfers. The four SPI bus signals are:

●

SPIRxD

Pin P1.5 or P4.5 receives data from the Slave SPI device to the uPSD34xx

●

SPITxD

Pin P1.6 or P4.6 transmits data from the uPSD34xx to the Slave SPI device

●

SPICLK

Pin P1.4 or P4.4 clock is generated from the uPSD34xx to the SPI Slave device

●

SPISEL

Pin P1.7 or P4.7 selects the signal from the uPSD34xx to an individual Slave SPI

device

This SPI interface supports single-Master/multiple-Slave connections. Multiple-Master

connections are not directly supported by the uPSD34xx (no internal logic for collision

detection).

If more than one Slave device is required, the SPISEL signal may be generated from

uPSD34xx GPIO outputs (one for each Slave) or from the PLD outputs of the PSD Module.

Figure 44 illustrates three examples of SPI device connections using the uPSD34xx:

●

Single-Master/Single-Slave with SPISEL

●

Single-Master/Single-Slave without SPISEL

●

Single-Master/Multiple-Slave without SPISEL

Figure 44.

SPI device connection examples

SPI Bus

SPITxD

SPIRxD

uPSD34xx

SPI Master

SPI Slave

Device

SPICLK

SPISEL

AI07853b

MOSI

MISO

SCLK

Single-Master/Single-Slave, with SPISEL

Single-Master/Single-Slave, without SPISEL

Single-Master/Multiple-Slave, without SPISEL

SPI Slave

Device

MOSI

MISO

SCLK

SPI Slave

Device

MOSI

MISO

SCLK

SPITxD

SPIRxD

uPSD34xx

SPI Master

SPI Slave

Device

SPICLK

SPITxD

SPIRxD

uPSD34xx

SPI Master

SPICLK

GPIO or PLD

MOSI

MISO

SCLK

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