PCA9535CD datasheet(11/32 Pages) NXP

11 / 32 page

PCA9535_PCA9535C_3

Product data sheet

Rev. 03 — 4 October 2007

11 of 32

NXP Semiconductors

PCA9535; PCA9535C

16-bit I2C-bus and SMBus, low power I/O port with interrupt

6.5.2 Reading the port registers

In order to read data from the PCA9535/PCA9535C, the bus master must ﬁrst send the

PCA9535/PCA9535C address with the least signiﬁcant bit set to a logic 0 (see Figure 6

“PCA9535; PCA9535C device address”). The command byte is sent after the address and

determines which register will be accessed. After a restart, the device address is sent

again, but this time the least signiﬁcant bit is set to a logic 1. Data from the register

deﬁned by the command byte will then be sent by the PCA9535/PCA9535C (see

Figure 10, Figure 11 and Figure 12). Data is clocked into the register on the falling edge of

the acknowledge clock pulse. After the ﬁrst byte is read, additional bytes may be read but

the data will now reﬂect the information in the other register in the pair. For example, if you

read Input Port 1, then the next byte read would be Input Port 0. There is no limitation on

the number of data bytes received in one read transmission but the ﬁnal byte received, the

bus master must not acknowledge the data.

Remark: Transfer can be stopped at any time by a STOP condition.

Fig 10. Read from register

START condition

R/W

acknowledge

from slave

002aac222

acknowledge

from slave

SDA

acknowledge

from master

DATA (first byte)

slave address

STOP

condition

(repeated)

START condition

(cont.)

A2 A1 A0

R/W

acknowledge

from slave

slave address

at this moment master-transmitter becomes master-receiver

and slave-receiver becomes slave-transmitter

no acknowledge

from master

COMMAND BYTE

A2 A1 A0

data from lower or

upper byte of register

LSB

MSB

DATA (last byte)

data from upper or

lower byte of register

LSB

MSB

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