LPC2364 datasheet(14/47 Pages) NXP

14 / 47 page

LPC2364_66_68_2

Preliminary data sheet

Rev. 02 — 1 October 2007

14 of 47

NXP Semiconductors

LPC2364/66/68

Fast communication chip

The Thumb set’s 16-bit instruction length allows it to approach twice the density of

standard ARM code while retaining most of the ARM’s performance advantage over a

traditional 16-bit processor using 16-bit registers. This is possible because Thumb code

operates on the same 32-bit register set as ARM code.

Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the

performance of an equivalent ARM processor connected to a 16-bit memory system.

7.2 On-chip ﬂash programming memory

The LPC2364/66/68 incorporate a 128 kB, 256 kB, and 512 kB ﬂash memory system

respectively. This memory may be used for both code and data storage. Programming of

the ﬂash memory may be accomplished in several ways. It may be programmed In

System via the serial port (UART0). The application program may also erase and/or

program the ﬂash while the application is running, allowing a great degree of ﬂexibility for

data storage ﬁeld and ﬁrmware upgrades.

The ﬂash memory is 128 bits wide and includes pre-fetching and buffering techniques to

allow it to operate at SRAM speeds of 72 MHz.

The LPC2364/66/68 provides a minimum of 100000 write/erase cycles and 20 years of

data retention.

7.3 On-chip SRAM

The LPC2364/66/68 includes a SRAM memory of 8 kB, 32 kB, and 32 kB respectively,

reserved for the ARM processor exclusive use. This RAM may be used for code and/or

data storage and may be accessed as 8 bits, 16 bits, and 32 bits.

A 16 kB SRAM block serving as a buffer for the Ethernet controller and an 8 kB SRAM

associated with the USB device can be used both for data and code storage, too.

Remaining SRAM such as a 4 kB USB FIFO and a 2 kB RTC SRAM can be used for data

storage only. The RTC SRAM is battery powered and retains the content in the absence of

the main power supply.

7.4 Memory map

The LPC2364/66/68 memory map incorporates several distinct regions as shown in

Figure 3.

In addition, the CPU interrupt vectors may be remapped to allow them to reside in either

ﬂash memory (default), boot ROM, or SRAM (see Section 7.25.6).

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