ADS1174IPAPR datasheet(25/35 Pages) TI

25 / 35 page

www.ti.com

BOUNDARY SCAN TEST[1:0] INPUTS

VCOM OUTPUT

NOTE:BufferisrequiredifVCOMisusedforanypurpose.

OPA350

0.1 F

VCOM

VDD/2)

ADS1174/ADS1178

ADS1174

ADS1178

SBAS373 – OCTOBER 2007

Therefore,

using

boundary

scan

tests,

the

ADS1174/78

digital

I/O

should

connect

The Boundary Scan test mode feature of the

JTAG-compatible device. The analog input, power

ADS1174/78 allows continuity testing of the digital I/O

supply, and ground pins remain connected as normal.

pins. In this mode, the normal functions of the digital

The test mode is engaged by the setting the pins

pins are disabled and routed to each other as pairs

TEST[1:0] = 11. For normal converter operation, set

through internal logic, as shown in Table 13. Note

TEST[1:0] = 00.

that some of the digital input pins become outputs.

Table 13. Test Mode Pin Map (TEST[1:0] = 11)

The VCOM pin is an analog output of approximately

TEST MODE PIN MAP(1)

AVDD/2. This voltage may be used to set the

INPUT PINS

OUTPUT PINS

common-mode voltage of the input buffers. However,

PWDN1

DOUT1

the pin must be buffered. A 0.1

μF capacitor to AGND

PWDN2

DOUT2

is recommended to reduce noise pick-up.

PWDN3

DOUT3

PWDN4

DOUT4

PWDN5 (2)

DOUT5(2)

PWDN6 (2)

DOUT6(2)

PWDN7 (2)

DOUT7(2)

PWDN8 (2)

DOUT8(2)

MODE

DIN

FORMAT0

CLKDIV

FORMAT1

DRDY/FSYNC

Figure 25. VCOM Output

FORMAT2

SCLK

(1)

The CLK input does not have a test output; SYNC = 1 and is

an output.

(2)

ADS1178 only.

Submit Documentation Feedback

Product Folder Link(s): ADS1174 ADS1178

ADS1174IPAPR bảng dữ liệu(PDF) 25 Page - Texas Instruments

ADS1174IPAPR bảng dữ liệu(HTML) 25 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

bảng dữ liệu tải về

Link URL