công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

Preview PDF HTML

ADS1174IPAPR bảng dữ liệu(PDF) 16 Page - Texas Instruments

Click here to check the latest version.
tên linh kiện ADS1174IPAPR
Giải thích chi tiết về linh kiện  Quad/Octal, Simultaneous Sampling, 16-Bit Analog-to-Digital Converters
PDF  35 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  TI [Texas Instruments]
Trang chủ  http://www.ti.com
Logo TI - Texas Instruments

ADS1174IPAPR bảng dữ liệu(HTML) 16 Page - Texas Instruments

Back Button ADS1174IPAPR Datasheet HTML 12Page - Texas Instruments ADS1174IPAPR Datasheet HTML 13Page - Texas Instruments ADS1174IPAPR Datasheet HTML 14Page - Texas Instruments ADS1174IPAPR Datasheet HTML 15Page - Texas Instruments ADS1174IPAPR Datasheet HTML 16Page - Texas Instruments ADS1174IPAPR Datasheet HTML 17Page - Texas Instruments ADS1174IPAPR Datasheet HTML 18Page - Texas Instruments ADS1174IPAPR Datasheet HTML 19Page - Texas Instruments ADS1174IPAPR Datasheet HTML 20Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 16 / 35 page
background image
www.ti.com
CLK
DRDY
SYNC
t
NDR
t
SYN
t
SCSU
t
CSHD
FSYNC
ValidData
DOUT
SYNC
t
NDR
t
SYN
CLK
t
CSHD
t
SCSU
ADS1174
ADS1178
SBAS373 – OCTOBER 2007
After
synchronization,
indication
of
valid
data
In the Frame-Sync format, DOUT goes low as soon
depends on the whether SPI or Frame-Sync format
as SYNC is taken low; see Figure 14. After SYNC is
was used.
returned high, DOUT stays low while the digital filter
is settling. Once valid data are ready for retrieval,
In the SPI format, DRDY goes high as soon as SYNC
DOUT begins to output valid data. For proper
is taken low; see Figure 13. After SYNC is returned
synchronization, FSYNC, SCLK, and CLK must be
high, DRDY stays high while the digital filter is
established before taking SYNC high, and must then
settling. Once valid data are ready for retrieval,
remain running.
DRDY goes low.
Figure 13. Synchronization Timing for SPI Protocol
Table 8. SPI Protocol
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tCSHD
CLK to SYNC hold time
10
ns
tSCSU
SYNC to CLK setup time
5
ns
tSYN
Synchronize pulse width
1
CLK periods
tNDR
Time for new data to be ready
129
Conversions (1/fDATA)
Figure 14. Synchronization Timing for Frame-Sync Protocol
Table 9. Frame-Sync Protocol
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tCSHD
CLK to SYNC hold time
10
ns
tSCSU
SYNC to CLK setup time
5
ns
tSYN
Synchronize pulse width
1
CLK periods
tNDR
Time for new data to be ready
127
128
Conversions (1/fDATA)
16
Submit Documentation Feedback
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): ADS1174 ADS1178



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35


bảng dữ liệu tải về

Go To PDF Page


Link URL



Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Liên kết đến bảng dữ liệu    |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com