STE2004SDIE2 datasheet(52/79 Pages) STMICROELECTRONICS

52 / 79 page

Instruction set

STE2004S

52/79

If the DIR bit is set to a logic 0, the offset register is increased by one and the raster is

scrolled from top down. If the DIR bit is set to a logic 1, the offset register is decreased by

one and the raster is scrolled from bottom-up.

5.6

Dual partial display

If the PE bit is set to a logic one the dual partial display mode is enabled. There are eight

partial display modes available. The offset of the two partial display zones is row by row

programmable. The icon row is accessed last in each partial display frame.

Two sets of register for the HV-generator parameters are provided (PRS[1:0], Vop[6:0],

BS[2:0], CP[2:0]), allowing normal mode and partial display mode to be switched using one

instruction. The HV generator is automatically reconfigured using the parameters related to

the enabled mode. The parameters of the two sets of registers with the same function are

located in the same position of the instruction set. The registers related to the normal mode

are accessible when normal mode (PE=0) is selected, the others are accessible when the

partial display mode is enabled (PE=1). To setup the PRS[1:0], Vop[6:0], BS[2:0], CP[2:0]

values, follow the instruction flow proposed in

Figure 54. To setup partial display sectors

start qddress and partial display mode no particular instruction flow has to be followed.

Figure 53.

Dual partial display enabling instruction flow

Table 23. Scrolling function

MUX Rate

Icon mode

Description

Icon row driver with MY=0

MUX 33

Icon row not scrooled

R48

MUX 33

33 line graphic matrix

R48

MUX 49

Icon row not scrooled

R56

MUX 49

49 line graphic matrix

R56

MUX 65

Icon row not scrooled

R64

MUX 65

65 line graphic matrix

R64

ENABLE DUAL PARTIAL DISPLAY

END OF ENABLING DUAL PARTIAL DISPLAY

SET PE=1

OPTIONAL1

SET 1st Sector Start Address

SET 2nd Sector Start Address

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