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PM6680 bảng dữ liệu(PDF) 37 Page - STMicroelectronics

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PM6680 bảng dữ liệu(HTML) 37 Page - STMicroelectronics

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7.13.6
Closing the integrator loop
The design of external feedback network depends on the output voltage ripple. If the ripple
is higher than approximately 30mV, the feedback network (Figure 35) is usually enough to
keep the loop stable.
Figure 36.
Circuitry for output ripple compensation
The stability of the system depends firstly on the output capacitor zero frequency. The
following condition should be satisfied:
Equation 23
where k is a design parameter greater than 3 and Rout is the ESR of the output capacitor. It
determinates the minimum integrator capacitor value CINT:
Equation 24
where gm = 50us is the integrator transconductance.
In order to ensure stability it must be also verified that:
Equation 25
+
-
V
Vrr
C
CO
OM
MP
P
g
gm
m
O
OU
UT
T
V
Vrr
+
P
PW
WM
M
C
Co
om
mp
pa
arra
atto
orr
C
CIIN
NT
T
R
RIIN
NT
T
C
CF
FIIL
LT
T
t
Vr
C
CO
OU
UT
T
COMP PIN
VOLTAGE
L
L
D
D
OUTPUT
VOLTAGE
I=gm(V1-Vr)
V
V1
1
t
?V
?V
V
VC
CIIN
NT
T
R
RO
OU
UT
T
F
FB
B
R
R1
1
R
R2
2
out
out
Zout
sw
R
C
2
k
f
k
f
×
×
π
=
×
>
OUT
Zout
sw
m
INT
V
Vr
f
k
f
2
g
C
×
⎟
⎠
⎞
⎜
⎝
⎛
−
×
π
>
OUT
Zout
m
INT
V
Vr
f
2
g
C
×
×
π
>



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