This Data Sheet may be revised by subsequent versions

©2004 Eon Silicon Solution, Inc., www.essi.com.tw

or modifications due to changes in technical specifications.

6

EN25F20

Rev. B, Issue Date: 2007/05/15

device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register

(SRP, BP1, BP0) become read-only bits.

In OTP mode, this bit is served as OTP_LOCK bit, user can read/program/erase OTP sector as normal

sector while OTP_LOCK value is equal 0, after OTP_LOCK is programmed with 1 by WRSR command,

the OTP sector is protected from program and erase operation. The OTP_LOCK bit can only be

programmed once.

Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to 1, user

must clear the protect bits before enter OTP mode and program the OTP code, then execute WRSR command

to lock the OTP sector before leaving OTP mode.

Write Protection

Applications that use non-volatile memory must take into consideration the possibility of noise and other

adverse system conditions that may compromise data integrity. To address this concern the EN25F20

provides the following data protection mechanisms:

while the power supply is outside the operating specification.

Program, Erase and Write Status Register instructions are checked that they consist of a number of

clock pulses that is a multiple of eight, before they are accepted for execution.

All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the

Write Enable Latch (WEL) bit . This bit is returned to its reset state by the following events:

–

Power-up

– Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction

completion or Page Program (PP) instruction completion or Sector Erase (SE)instruction

completion or Block Erase (BE) instruction completion or Chip Erase (CE) instruction completion

The Block Protect (BP1, BP0) bits allow part of the memory to be configured as read-only. This is

the Software Protected Mode (SPM).

The Write Protect (WP#) signal allows the Block Protect (BP1, BP0) bits and Status Register Protect

(SRP) bit to be protected. This is the Hardware Protected Mode (HPM).

In addition to the low power consumption feature, the Deep Power-down mode offers extra software

protection from inadvertent Write, Program and Erase instructions, as all instructions are ignored

except one particular instruction (the Release from Deep Power-down instruction).

TABLE 3. Protected Area Sizes Sector Organization

Status Register

Content

Memory Content

BP1

Bit

BP0

Bit

Protect Blocks

Addresses

Density(KB)

Portion

1

1

All ( Block 0 to 3)

000000h-03FFFFh

256KB

All Block

1

0

Block 2 to 3

020000h-03FFFFh

128KB

Upper 1/2

0

1

Block 3

030000h-03FFFFh

64KB

Upper 1/4

0

0

None

None

None

None

Hold Function

The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the

clocking sequence. However, taking this signal Low does not terminate any Write Status Register,

Program or Erase cycle that is currently in progress.

To enter the Hold condition, the device must be selected, with Chip Select (CS#) Low. The Hold condition

starts on the falling edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (CLK)

being Low (as shown in Figure 4.).

The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this coincides with

Serial Clock (CLK) being Low.