MPC8280 datasheet(1259/1386 Pages) FREESCALE

1259 / 1386 page

Fast Ethernet Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

36-25

Data length is the number of octets the CP writes into this BD data buffer. It is written by the CP as the

buffer is closed. When this BD is the last BD in the frame (RxBD[L] = 1), the data length contains the total

number of frame octets (including four bytes for CRC). Note that at least as much memory should be

allocated for each receive buffer as the size specified in MRBLR. MRBLR should be divisible by 32 and

not less than 64.

The receive buffer pointer, which points to the first location of the associated data buffer, can reside in

external memory. This value must be divisible by 16.

When a received frame’s data length is an exact multiple of MRBLR, the last BD contains only the status

and total frame length.

NOTE

At least two BDs must be prepared before beginning reception.

Broadcast address. Valid only for the last buffer in a frame (RxBD[L] = 1). The received frame

address is the broadcast address.

Multicast address. Valid only for the last buffer in a frame (RxBD[L] = 1). The received frame address

is a multicast address other than a broadcast address.

Rx frame length violation. A frame length greater than the MFLR (maximum frame length) defined

for this FCC is recognized.

Rx nonoctet aligned frame. A frame that contained a number of bits not divisible by eight is received

and the CRC check at the preceding byte boundary generated an error.

Short frame. A frame length less than the MINFLR (minimum frame length) defined for this channel

is recognized. This indication is possible only if the FPSMR[RSH] = 1.

Rx CRC error. This frame contains a CRC error.

Overrun. A receiver overrun occurred during frame reception.

Collision. This frame is closed because a collision occurred during frame reception. Set only if a late

collision occurs or if FPSMR[RSH] is set. The late collision definition is determined by the setting of

FPSMR[LCW].

Table 36-10. RxBD Field Descriptions (continued)

Bits

Name

Description

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